Schematic-Driven Extracted Views for Editable Simulation
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Solution Overview
Problem
Conventional electronic design verification methods, such as SPICE simulations, are computationally expensive and time-consuming, especially for complex designs, and struggle with troubleshooting distributed pins and vector pins, as they require multiple iterations between schematic and layout edits, losing hierarchical structure and requiring non-editable, unreadable simulation views.
Innovation Solution
Implementing schematic-driven extracted views that generate models from the schematic design, preserving hierarchical structure and allowing direct editing and analysis, without regenerating from the layout, using models like SPICE sub-circuits and IBIS models, interconnected with layout connectivity information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional layout extracted views are generated from the finished layout by identifying corresponding schematic symbols, then the simulation view can be created, but the view becomes non-editable and loses hierarchical structure, requiring multiple iterations between schematic and layout edits
Solution Approach 1:
Instead of extracting the simulation view from the layout (conventional approach), the patent inverts the process by generating the simulation view directly from the schematic design. This allows the simulation view to remain editable and maintain hierarchical structure, eliminating the need for multiple iterations between schematic and layout edits.
Solution Approach 2:
The patent creates a copy of the schematic design to generate the simulation view, rather than extracting from the layout. This copy can be edited independently while maintaining the connection to the original schematic, enabling direct modification without regenerating from layout.
2Reliability
If SPICE simulations are performed on complex electronic designs, then verification can be achieved, but the process becomes computationally expensive and time-consuming
Solution Approach 1:
The patent extracts only the necessary portions of the electronic design into separate simulation views, rather than simulating the entire complex design at once. This extraction allows for targeted verification of specific circuits or components, reducing computational overhead while maintaining verification accuracy.
Solution Approach 2:
The patent segments the electronic design into multiple hierarchical simulation views, allowing different portions to be simulated independently or in combination. This segmentation reduces the computational complexity of simulating entire complex designs while maintaining verification reliability.
3Device complexity
If distributed pins or vector pins are represented as single input pins in schematic symbols, then the schematic can be simplified, but troubleshooting becomes difficult as designers must guess which pin is causing abnormal behavior
Solution Approach 1:
The patent makes the simulation view dynamic by allowing designers to expand distributed pins and vector pins from their simplified single-pin representation into their full multi-pin configurations during troubleshooting. This dynamic expansion maintains schematic simplicity while enabling detailed troubleshooting when needed.
Solution Approach 2:
The patent introduces an intermediary layer between the simplified schematic symbol and the detailed pin configurations. This intermediary allows the schematic to remain simple while providing a pathway to expand and examine individual pins during troubleshooting, eliminating the need to guess which pin is problematic.
4Loss of information
If the extracted view is generated from the layout, then connectivity information can be obtained, but the view cannot be edited without regenerating from layout, losing hierarchical structure
Solution Approach 1:
The patent inverts the conventional extraction process by generating the simulation view from the schematic design rather than from the layout. This inversion preserves the hierarchical structure inherent in schematic designs and enables editing without requiring regeneration from layout, as the simulation view is directly derived from the editable schematic.
Data Source
AI summary
Disclosed are methods, systems, and articles of manufacture for implementing schematic driven extracted views for an electronic design. These techniques identify a schematic circuit component design represented by a schematic symbol from a schematic design and identifying layout device information from a layout of the electronic design. An extracted view is generated anew or updated from an existing extracted view at least by placing and interconnecting a symbol in the schematic design based at least in part upon the layout device information. The electronic design may be further updated based in part or in whole upon results of performing one or more analyses on the extracted view.