Schematic Overlay for IC Design Verification
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Solution Overview
Problem
The design and verification of integrated circuits face challenges in modifying testbench schematics, as it is difficult to differentiate between permanent and temporary changes, leading to synchronization issues and errors, especially during post-layout analysis where the testbench lacks a physical layout representation.
Innovation Solution
The use of overlay schematic data allows for modifying a base circuit design without altering the base schematic data, by generating schematic overlay data that represents changes, enabling EDA operations while keeping the base data unchanged, and employing visualization techniques to distinguish modified elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the base schematic data is modified directly to implement temporary test changes, then the verification and debugging process becomes simpler, but it becomes difficult to differentiate between permanent design modifications and temporary test modifications, leading to synchronization issues and errors
Solution Approach 1:
The patent segments the modification process by introducing overlay schematic data as a separate layer that sits on top of the base schematic data. This allows test modifications to be made in the overlay layer without directly altering the base schematic data, thereby maintaining clear differentiation between permanent designs and temporary test changes while preserving data integrity.
Solution Approach 2:
The overlay schematic data acts as an intermediary between the designer and the base schematic data. Instead of directly modifying the base schematic, all temporary test modifications are made through the overlay layer, which mediates the changes and prevents direct contamination of the original design data.
2Reliability
If the base schematic data is copied to a new library to make temporary changes, then the base design data remains unchanged, but synchronization issues arise when the base design data changes and the copied data must be manually updated
Solution Approach 1:
The overlay schematic data is nested within the context of the base schematic data, creating a hierarchical relationship where the overlay layer contains the temporary modifications while referencing the underlying base schematic. This nested structure allows the overlay to inherit updates from the base automatically while maintaining its own separate modification layer.
Solution Approach 2:
Instead of copying the entire base schematic to a new library, the patent creates a lightweight overlay schematic that copies only the necessary modification information. This overlay can be applied to the base schematic on-demand, eliminating the need for manual synchronization of entire schematic copies while still preserving the ability to make temporary changes.
3Adaptability or versatility
If a testbench schematic is created separately from the layout hierarchy, then test modifications can be made independently, but post layout analysis tools cannot properly analyze the testbench because it lacks a physical layout representation
Solution Approach 1:
The patent merges the overlay schematic data with the base schematic data to create a unified modified schematic that combines both the original design and temporary test modifications. This merged schematic maintains the layout hierarchy connection, allowing post-layout analysis tools to properly analyze the complete circuit including testbench elements while preserving the independence of test modifications through the overlay mechanism.
Data Source
AI summary
Embodiments relate to schematic overlays describing modification to a base design for exploring modification or verification of the base design. Test circuitry may be modified or inserted without effecting the change in a base design schematics. The modifications to the base design schematics are also highlighted in views at a level of hierarchy where the modifications were made as well as at a higher levels of circuit abstraction. By using schematic overlays, modification to the base design can be avoided while creating a testbench.