Schmitt Trigger Buffer Circuit for Low-Harmonic Clock Switching
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Solution Overview
Problem
High frequency switching circuits in portable terminals face issues with harmonic noise generation due to the high frequency of clock signals, which interferes with the high frequency signals being switched, leading to increased noise levels and potential mis-operation in multi-mode/multi-band operations.
Innovation Solution
A buffer circuit with a Schmitt trigger type inverter circuit and impedance elements is used to shape the clock signal, reducing harmonic noise by gentler waveform output and minimizing delay time, while an SOI substrate reduces signal leakage, and a series-parallel converter with D-type flip-flops converts serial control signals to parallel, synchronizing with the clock signal to suppress harmonic noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high frequency clock signal is used for series-parallel conversion, then the conversion speed is improved, but harmonic noise is generated that interferes with high frequency signals
Solution Approach 1:
A buffer circuit is introduced as an intermediary component between the clock signal source and the series-parallel converter. This buffer circuit shapes the clock signal waveform to reduce harmonic content while maintaining the required signal frequency for fast conversion, thus mediating between speed requirements and noise generation
Solution Approach 2:
The waveform characteristics of the clock signal are modified by changing its rise and fall times through the buffer circuit. By adjusting these temporal parameters, the spectral content is altered to suppress harmonics near the high frequency signal band while preserving the fundamental frequency needed for conversion operations
2Adaptability or versatility
If the number of ports in high frequency switching circuit is increased for multi-mode/multi-band operation, then the adaptability is improved, but the number of control signal terminals increases
Solution Approach 1:
The control signal is segmented from parallel to serial form, allowing multiple control bits to be transmitted sequentially through a single terminal rather than requiring multiple simultaneous terminals. This segmentation enables multi-port switching capability while reducing the physical terminal count
Solution Approach 2:
Serial control signals are transmitted periodically synchronized with the clock signal, allowing multiple control operations to be performed in sequence through a single terminal. The periodic clocked operation enables time-multiplexed control of multiple switching ports
3Speed
If rise time and fall time of clock signal are reduced for faster conversion, then the conversion speed is improved, but harmonic content increases
Solution Approach 1:
The buffer circuit modifies the temporal parameters of the clock signal by controlling its rise and fall times. This parameter adjustment shapes the waveform to achieve an optimal balance between transition speed (affecting conversion performance) and spectral content (affecting harmonic generation), resolving the contradiction between speed and harmonic content
Data Source
AI summary
A buffer circuit includes a first inverter circuit that inverts an input signal, a second inverter circuit that inverts the output signal of the first inverter circuit, an impedance element connected between the first inverter circuit and the second inverter circuit, a first conductivity type switching element that increases a potential of the output node of the second inverter circuit when the input signal exceeds a first threshold voltage, and a second conductivity type switching element that decreases a potential of the output node of the second inverter circuit when the input signal is lower than a second threshold voltage.