Schmitt Trigger Circuit With Adjustable Trip Points for Level Detection

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Solution Overview

Problem

Conventional Schmitt triggers are not suitable for use in power-detecting modules due to trip points that are not adjustable enough, typically ranging from 0.3 Vcc to 0.7 Vcc, which is not sufficient for accurate power voltage detection in multi-domain-voltage island designs.

Innovation Solution

A Schmitt trigger design with a specific configuration of PMOS and NMOS transistors, including feedback transistors and a switch control unit, allows for adjustable trip points between 0.1 Vcc and 0.9 Vcc, enabling accurate level detection in power-detecting modules.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a conventional Schmitt trigger is used for level detection, then the circuit structure is simple, but the trip points are fixed and cannot be adjusted to the required range (0.1 Vcc to 0.9 Vcc)

Engineering Contradiction:
Improvetrip point adjustabilityVSAvoidcircuit structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The Schmitt trigger circuit is segmented into multiple PMOS transistors (first PMOS transistors with drains and sources serially connected) and multiple NMOS transistors (first NMOS transistors with drains and sources serially connected). This segmentation allows for creating multiple tap points in the circuit where feedback can be applied at different stages, enabling adjustable trip points across a wider voltage range (0.1 Vcc to 0.9 Vcc) while maintaining a systematic and organized circuit structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Second PMOS transistors and second NMOS transistors are introduced as feedback transistors that act as intermediaries. These feedback transistors connect between ground and intermediate nodes (or voltage source and intermediate nodes) and have gates coupled to the output end. They mediate the feedback signal to adjust the trip points dynamically, providing the necessary adaptability without requiring a complete redesign of the basic Schmitt trigger structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If the number of PMOS and NMOS transistors is increased to achieve adjustable trip points, then the trip point range expands, but the circuit complexity increases

Engineering Contradiction:
Improvetrip point rangeVSAvoidtransistor count
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The circuit design uses multiple PMOS transistors and NMOS transistors that serve dual functions: the first set of transistors form the main amplification path while the second set provide feedback control. This multi-functionality allows the same transistor types to perform different roles within the circuit, expanding the trip point adjustment capability without requiring entirely separate circuit blocks for each function, thereby controlling overall complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The circuit incorporates feedback transistors (second PMOS and NMOS transistors) whose gates are coupled to the output end, creating dynamic feedback paths. This dynamic configuration allows the trip points to be adjusted based on output conditions, providing adaptability and expandable trip point range while using a manageable number of transistors through intelligent circuit topology rather than brute-force addition of components.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS7764101B2Schmitt-trigger-based level detection circuit
Publication Date: 2010.07.27 FARADAY TECH CORP
  • US7764101B2 patent drawing
  • US7764101B2 patent drawing
  • US7764101B2 patent drawing

AI summary

A Schmitt trigger includes A first PMOS transistors having the drains and sources thereof serially connected and coupled between a voltage source and an output end, and having gates thereof coupled to an input end; B first NMOS transistors having the drains and sources thereof serially connected and coupled between the output end and ground, and having gates thereof coupled to the input end; C second PMOS transistors, each being coupled between ground and a node between the drain and the source of the first PMOS transistors and having the gate thereof coupled to the output end; and D second NMOS transistors, each being coupled between the voltage source and a node between the drain and the source of the first NMOS transistors and having the gate thereof coupled to the output end. A is greater than 2 and C, and B is greater than 2 and D.