Programmable Schmitt Trigger Delay Control Without Added Logic Gates

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Solution Overview

Problem

Existing methods for introducing controllable delays in circuit paths, such as adding logic gates or using transistors and capacitors, are costly and complex, necessitating the need for more efficient delay control mechanisms.

Innovation Solution

The use of a Schmitt trigger circuit with a small transistor count to vary the trip point of an inverter, where the feedback strength is programmable to adjust the delay, allowing for faster delay control without increasing the full gate delay.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If additional logic gates are added to an input-output path to introduce controllable delays, then the delay control capability is improved, but the circuit complexity and cost increase

Engineering Contradiction:
Improvedelay control capabilityVSAvoidcircuit complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent changes the threshold voltage parameter of the inverter by introducing a Schmitt trigger circuit with adjustable feedback. The feedback ratio is controlled by a programmable parameter (such as a control signal or digital code) that adjusts the trip point voltage, thereby controlling the delay time without adding logic gates. This parameter-based control achieves delay adjustment while maintaining simple circuit structure.

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If a transistor coupled to a capacitor is used to slow down signal transition, then the delay control is achieved, but the die area cost increases

Engineering Contradiction:
Improvedelay controlVSAvoiddie area
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent extracts and eliminates the capacitor component from the delay control mechanism. Instead of using a transistor-capacitor RC circuit that occupies significant die area, the invention uses only transistors configured as a Schmitt trigger with feedback. The delay is achieved through the feedback mechanism adjusting the inverter's trip point, completely removing the need for capacitors and thereby reducing die area consumption.

Inventive Principle:
Principle #2Taking out (Extraction)

3Adaptability or versatility

If the feedback strength of the Schmitt trigger is increased to adjust delay, then the delay adjustment range is improved, but the transistor switching speed decreases

Engineering Contradiction:
Improvedelay adjustment rangeVSAvoidtransistor switching speed
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent implements dynamic feedback strength adjustment where the feedback ratio can be programmably changed based on requirements. The feedback network uses transistors whose effective resistance or coupling strength can be dynamically controlled by gate voltages or control signals. This allows the system to adapt the feedback strength: stronger feedback for larger delay ranges, weaker feedback for faster switching, optimizing both delay adjustment capability and switching speed根据不同应用场景动态调整。

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS8502564B2Adjustable Schmitt trigger
Publication Date: 2013.08.06 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US8502564B2 patent drawing
  • US8502564B2 patent drawing
  • US8502564B2 patent drawing

AI summary

A circuit comprises an inverter, a first transistor, a second transistor, and at least one switching circuit. The inverter has a first node and a second node. The first transistor has a first terminal, a second terminal, and a third terminal. The second transistor has a fourth terminal, a fifth terminal, and a sixth terminal. The at least one switching circuit is configured to switch a connection of at least one of the first transistor and the second transistor to the inverter. The second terminal and the fifth terminal are coupled to the first node. The third terminal and the sixth terminal are coupled to the second node. The first transistor and the second transistor are configured to cause a plurality of time delays at the second node.