Schmitt Trigger Circuit Layout for Higher IC ESD Breakdown
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) become smaller and more complex, they face challenges with reduced operating voltages, which increase susceptibility to electrostatic discharge (ESD) and affect overall IC performance.
Innovation Solution
The integration of a Schmitt trigger circuit coupled in parallel with an ESD circuit, featuring specific transistor configurations and feedback mechanisms, helps prevent parasitic transistors from turning on during ESD events, thereby enhancing ESD performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If operating voltage is reduced to enable smaller and more complex ICs, then device integration and complexity are improved, but susceptibility to electrostatic discharge increases
Solution Approach 1:
The ESD protection function is segmented from the main circuit operation. The circuit is divided into normal operating mode (Schmitt trigger functionality) and ESD protection mode (parasitic transistor activation), allowing the same circuit structure to serve dual purposes without interfering with each other during respective operating conditions.
Solution Approach 2:
The parasitic transistors serve as intermediary protection elements that activate only during ESD events. These transistors act as a mediator between the ESD threat and the sensitive low-voltage circuit, providing a discharge path for ESD current while remaining inactive during normal operation to avoid affecting circuit performance.
2Reliability
If traditional ESD protection methods are used, then ESD protection is provided, but breakdown voltage is limited and performance is reduced
Solution Approach 1:
The ESD protection function is merged with the Schmitt trigger circuit by utilizing the inherent parasitic transistors present in the CMOS structure. This combination eliminates the need for separate ESD protection circuits, allowing the same transistors to provide both circuit functionality and ESD protection, thereby achieving higher breakdown voltage without sacrificing normal circuit performance.
Solution Approach 2:
The parasitic transistors in the CMOS Schmitt trigger circuit serve multiple functions: they are part of the normal circuit operation during low-voltage mode and simultaneously provide ESD protection during high-voltage ESD events. This multi-functionality allows a single circuit structure to achieve both operational requirements and protection requirements.
Data Source
AI summary
A Schmitt trigger circuit includes a first and second set of transistors, a first and second feedback transistor, and a first and second circuit. The first set of transistors is connected between a first voltage supply and an output node. The first voltage supply has a first voltage. The second set of transistors is connected between the output node and a second voltage supply. The second voltage supply has a second voltage. The first feedback transistor is connected to the output node, a first node and a second node. The second feedback transistor is connected to the output node, a third node and a fourth node. The first circuit is coupled to and configured to supply the second supply voltage to the second node. The second circuit is coupled to and configured to supply the first supply voltage to the fourth node.