Schottky Junction Diode CMOS Fabrication
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Solution Overview
Problem
Conventional CMOS semiconductor fabrication processes do not support the fabrication of Schottky junction diodes, leading to high capacitance issues that limit the performance of these devices.
Innovation Solution
A Schottky junction diode device is fabricated in a conventional CMOS process by separating p− and n− wells, with a metal-containing region forming a Schottky junction at an interface within the n− well, and a second well is disposed over the substrate without direct contact to reduce junction capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Schottky junction diodes are fabricated using conventional semiconductor processes with p- and n- wells in direct contact, then the device structure is simple and manufacturing is easier, but the junction capacitance is high which limits performance
Solution Approach 1:
The patent divides the semiconductor structure into four distinct regions: p-substrate, n-well, p-well, and n-well contact, separating the p- and n- wells so they are not in direct contact. This segmentation reduces the capacitance between opposite-type wells while maintaining the Schottky junction functionality, thereby improving device performance without excessive complexity
Solution Approach 2:
The patent applies different doping concentrations and types to specific regions: the n-well is doped to a first concentration, the p-well to a second concentration, and the n-well contact to a third concentration. This local differentiation of material properties optimizes the electrical characteristics and reduces capacitance in critical areas while maintaining overall device functionality
2Ease of manufacture
If Schottky junction diodes are fabricated in conventional CMOS processes, then manufacturing complexity is reduced and ease of manufacture improves, but standard CMOS processes do not natively support Schottky junction fabrication
Solution Approach 1:
The patent integrates Schottky junction diode fabrication into the standard CMOS fabrication process sequence, making the specialized Schottky process compatible with universal CMOS manufacturing. The method uses conventional CMOS steps (oxidation, deposition, photolithography, etching, ion implantation) to create both CMOS devices and Schottky diodes in the same process flow, achieving multi-functionality
Solution Approach 2:
The patent modifies specific process parameters within the CMOS fabrication sequence to enable Schottky junction formation. This includes adjusting doping concentrations and types at different stages, controlling metal layer deposition to create Schottky contacts, and timing the formation of the metal-containing layer relative to other process steps, thereby adapting the process without requiring a completely new fabrication methodology
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces junction capacitance, enabling improved performance of Schottky junction diodes and allowing them to be fabricated within conventional CMOS processes.
Implementation Method 1
A region of metal-containing material is disposed in the first well to form a Schottky junction at an interface between the region of metal-containing material and the first well
Data Source
AI summary
A Schottky junction diode device having improved performance is fabricated in a conventional CMOS process. A substrate including a material doped to a first conductivity type is formed. A first well is disposed over the substrate. The first well includes a material doped to a second conductivity type opposite that of the first conductivity type. A region of metal-containing material is disposed over the first well to form a Schottky junction at an interface between the region of metal-containing material and the first well. In one embodiment, a first well contact is disposed in a portion of the first well. A second well is disposed over the substrate wherein the second well includes a material doped to the first conductivity type. In one embodiment, the first well and the second well are not in direct contact with one another.