Schottky Diode Isolation Structure for Low Leakage Switching
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Solution Overview
Problem
Current semiconductor devices with Deep Trench Isolation (DTI) structures face challenges in achieving optimal isolation and performance for high-voltage lateral MOS transistors, particularly in terms of reducing leakage current and enhancing switching speed while maintaining low forward voltage drop.
Innovation Solution
The semiconductor device incorporates a trench insulating structure that penetrates through a pn-junction portion, a barrier forming region with a metal layer forming a Schottky-junction, and a cathode region, along with a guard region and shallow trench insulating structure, to effectively isolate the diode region and improve switching characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a Deep Trench Isolation (DTI) structure is used to isolate high-voltage lateral MOS transistors, then isolation performance is improved, but reverse leakage current increases and switching speed decreases
Solution Approach 1:
The isolation structure is segmented into multiple functional regions: the DTI structure provides primary isolation, while the guard ring structure with alternating n-type and p-type regions provides secondary isolation and leakage control. This segmentation allows each part to optimize for its specific function without compromising overall performance.
Solution Approach 2:
The guard ring structure acts as an intermediary element between the DTI structure and the active device regions. It mediates the electrical field distribution and provides an additional barrier against leakage current while maintaining the isolation benefits of the DTI structure.
2Reliability
If a Deep Trench Isolation (DTI) structure is used to isolate high-voltage lateral MOS transistors, then isolation performance is improved, but switching speed decreases
Solution Approach 1:
The guard ring structure introduces local quality variations with alternating n-type and p-type regions positioned strategically around the device. This local differentiation optimizes the electrical field distribution in critical areas, enabling faster switching while maintaining isolation.
Solution Approach 2:
The guard ring structure dynamically manages the electrical field during switching transitions, allowing rapid charge/discharge cycles while the DTI structure maintains static isolation. This dynamic control improves switching speed without sacrificing isolation performance.
3Object-generated harmful factors
If the trench insulating structure penetrates through the pn-junction portion to isolate the diode region, then reverse leakage current is reduced, but forward voltage drop increases
Solution Approach 1:
The trench insulating structure penetrates partially through the pn-junction portion rather than completely, providing sufficient isolation to reduce leakage current while maintaining adequate conduction paths for forward current, thus balancing leakage reduction with forward voltage characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces reverse leakage current, achieves low forward voltage, and enhances switching speed, thereby improving the overall performance and efficiency of the semiconductor device.
Implementation Method 1
a metal layer located on the principal surface such that the metal layer covers the barrier forming region in the diode region, and forming a Schottky-junction portion with the n-type semiconductor layer
Data Source
AI summary
A semiconductor device includes a chip having a principal surface, a pn-junction portion extending in a horizontal direction along the principal surface inside the chip, a trench insulating structure formed in the principal surface such that the trench insulating structure penetrates through the pn-junction portion, and demarcating a diode region in the chip, a barrier forming region formed in a surface layer portion of the principal surface in the diode region, and a metal layer located on the principal surface such that the metal layer covers the barrier forming region in the diode region, and forming a Schottky-junction portion with the barrier forming region.


