Schottky FET Gate Last Process Thin Channel Fabrication
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Scaling down field effect transistors (FETs) to achieve higher integration density in integrated circuits is challenging due to difficulties in achieving precise semiconductor thickness, particularly in the channel region, which affects the formation of silicide regions and leads to issues like silicide encroachment and delamination.
Innovation Solution
A method involving a gate last process where the semiconductor material in the source and drain regions is initially formed thick enough for easy silicide formation, and then the channel region is thinned using a sequential ozone modified Huang cleaning process to achieve precise control of thickness, allowing for a channel thickness of up to 7 nm.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the semiconductor material thickness is reduced to achieve sub-15 nm FETs, then integration density is improved, but manufacturing precision deteriorates due to difficulty in achieving precise thickness control
Solution Approach 1:
The source and drain regions are formed with sufficient silicon thickness before the channel region thinning process. This preliminary thick formation ensures that silicide regions can be properly formed without encroachment or delamination issues, while the channel region is subsequently thinned to the target thickness of 7 nm or less through selective removal processes.
Solution Approach 2:
Different thicknesses are applied to different regions of the semiconductor layer. The source and drain regions maintain greater thickness to support silicide formation, while the channel region is selectively thinned to 7 nm or less. This local differentiation allows each region to have the optimal thickness for its specific function.
2Length of moving object
If the silicon thickness in source and drain regions is reduced, then device scaling is improved, but reliability deteriorates due to silicide encroachment and delamination problems
Solution Approach 1:
The source and drain regions are formed with sufficient silicon thickness before the channel region thinning process. This preliminary thick formation ensures that silicide regions can be properly formed without encroachment or delamination issues, while the channel region is subsequently thinned to the target thickness of 7 nm or less through selective removal processes.
3Reliability
If epitaxial growth is used to build up source and drain semiconductor material, then silicide formation reliability is improved, but device complexity increases due to difficulty in growing on thin layers
Solution Approach 1:
Instead of building up source and drain material through epitaxial growth on thin layers (which is difficult), the approach is inverted: the semiconductor layer is formed with sufficient thickness first, then selectively thinned in the channel region. This avoids the complexity of epitaxial growth on sub-5 nm layers while achieving the same reliability outcome.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of FETs with a thin channel region and thick source and drain regions, improving electrostatic control and reducing parasitic resistance and capacitance, thus facilitating the production of sub-15 nm FETs with better integration density.
Implementation Method 1
a sequential ozone modified Huang cleaning process to achieve precise control of thickness
Data Source
AI summary
A field effect transistor (FET) includes a semiconductor on insulator substrate, the substrate comprising a top semiconductor layer; source and drain regions located in the top semiconductor layer; a channel region located in the top semiconductor layer between the source region and the drain region, the channel region having a thickness that is less than a thickness of the source and drain regions; a gate located over the channel region; and a supporting material located over the source and drain regions adjacent to the gate.