Schottky Gate Layout for Lower Capacitance and Field Concentration
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Solution Overview
Problem
Existing methods for manufacturing semiconductor devices face challenges in simultaneously relaxing electric field concentration and reducing electrostatic capacitance.
Innovation Solution
A method involving the formation of a gate electrode with specific side surface angles and differential etching rates for insulating films to create openings that allow the gate electrode to extend more towards the drain electrode, thereby relaxing electric field concentration and reducing electrostatic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the portion of the gate electrode extending on the insulating film toward the source electrode is made large, then the electrostatic capacitance between the gate electrode and channel becomes large, but the electric field concentration is reduced
Solution Approach 1:
The patent applies asymmetry by making the gate electrode width asymmetric: the portion extending toward the drain electrode is made larger than the portion extending toward the source electrode. This asymmetric configuration allows the gate electrode to effectively relax electric field concentration at the drain side while minimizing the increase in electrostatic capacitance by keeping the source side extension smaller.
Solution Approach 2:
The patent applies local quality by differentiating the gate electrode width at different locations. The gate electrode has a larger width on the drain electrode side and a smaller width on the source electrode side, allowing each portion to serve its specific function: the larger drain side portion relaxes electric field concentration, while the smaller source side portion minimizes capacitance increase.
2Reliability
If the gate electrode is extended to relax electric field concentration, then electric field distribution is improved, but the electrostatic capacitance increases
Solution Approach 1:
The patent resolves this contradiction by implementing asymmetric gate electrode extension where the width toward the drain electrode is larger than toward the source electrode. This asymmetric design provides the necessary gate electrode extension to relax electric field concentration at the drain side while limiting the extension toward the source side to minimize capacitance increase.
Solution Approach 2:
The patent applies local quality by creating different gate electrode widths at different locations along the channel. The local width toward the drain electrode is increased to improve electric field distribution, while the local width toward the source electrode is kept smaller to control the overall capacitance, thus achieving location-specific optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the simultaneous relaxation of electric field concentration and reduction of electrostatic capacitance in semiconductor devices, enhancing device performance.
Implementation Method 1
an etching rate of the second insulating film is higher than an etching rate of the first insulating film during the etching of the forming the first gate opening
Implementation Method 2
forming a gate electrode on the first insulating film and the second insulating film, the gate electrode making a Schottky contact with the semiconductor layer through the first gate opening and the second gate opening
Data Source
AI summary
A method for manufacturing a semiconductor device, includes forming source and drain electrodes on a semiconductor layer provided above a substrate; forming a first insulating film covering a surface of the semiconductor layer, between the source and drain electrodes, forming a second insulating film on the first insulating film, forming a mask on the second insulating film, the mask having an opening between the source and drain electrodes in a plan view viewed in a direction perpendicular to a substrate surface, forming a first gate opening in the first insulating film and forming a second gate opening in the second insulating film, by etching the first and second insulating films through the opening, and forming a gate electrode on the first and second insulating films, the gate electrode making a Schottky contact with the semiconductor layer through the first and second gate openings.