Gate-Controlled Schottky Semiconductor Structure for Low On-Resistance

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Solution Overview

Problem

Existing semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), face challenges in achieving low on-resistance due to high contact resistance at Schottky junctions, which limits their switching efficiency.

Innovation Solution

The semiconductor device incorporates a conductive portion forming a Schottky junction with a thinned region and an ohmic junction with a top region of higher impurity concentration, controlled by a gate electrode potential to switch between on and off states, reducing on-resistance through optimized junctions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a Schottky junction is formed between a conductive portion and a semiconductor layer, then the device can achieve switching function, but the contact resistance becomes high which increases on-resistance

Engineering Contradiction:
Improveswitching functionVSAvoidcontact resistance
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies local quality by creating a vertical impurity concentration gradient within the semiconductor layer. The impurity concentration is higher near the conductive portion interface and decreases toward the gate electrode, forming a localized high-concentration region that reduces contact resistance at the Schottky junction while preserving the switching function. This non-uniform doping profile optimizes electrical properties at specific locations without compromising overall device performance.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the impurity concentration parameter vertically through the semiconductor layer. By controlling the impurity concentration to be higher in the region adjacent to the conductive portion and lower near the gate electrode, the patent modifies the electrical characteristics locally to reduce contact resistance while maintaining the necessary field effect transistor operation. This parameter gradient approach resolves the contradiction between achieving low contact resistance and maintaining switching capability.

Inventive Principle:
Principle #35Parameter changes

2Object-affected harmful factors

If the impurity concentration is increased to reduce contact resistance, then on-resistance decreases, but the switching characteristics may be degraded

Engineering Contradiction:
Improveon-resistanceVSAvoidswitching characteristics
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The patent implements local quality by spatially differentiating the impurity concentration within the semiconductor layer. The high impurity concentration is localized to the region near the conductive portion to reduce contact resistance, while the region near the gate electrode maintains lower impurity concentration to preserve switching characteristics. This localized optimization allows simultaneous achievement of low on-resistance and good switching performance.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent segments the semiconductor layer into regions with different impurity concentrations. The lower impurity concentration region near the gate electrode handles switching operations, while the higher impurity concentration region near the conductive portion handles current conduction. This segmentation allows each region to be optimized for its specific function, resolving the trade-off between on-resistance and switching characteristics.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces on-resistance by enhancing current flow through ohmic junctions, improving switching efficiency and performance of the semiconductor device.

Implementation Method 1

a control electrode 13 provided in the semiconductor layer 2 via an insulating region 50; a first conductive portion 31 facing the control electrode 13 in a second direction orthogonal to a first direction oriented from the first electrode 11 to the second electrode 12, electrically connected to the second electrode 12, and having a first work function; a first semiconductor region 21 of a first conductivity type provided in the semiconductor layer 2, sandwiched between the insulating region 50 and the first conductive portion 31, and forming a Schottky junction with the first conductive portion 31

Methodology Applied
Scientific EffectSchottky barrier: Electrical Resistance

Implementation Method 2

controlled by a gate electrode potential to switch between on and off states

Methodology Applied
Scientific EffectField effect: Electric Field

Implementation Method 3

enhancing current flow through ohmic junctions

Methodology Applied
Scientific EffectOhmic junction: Conduction (electrical)

Data Source

PatentUS20250311289A1Semiconductor device and manufacturing method therefor
Publication Date: 2025.10.02 KK TOSHIBA
  • US20250311289A1 patent drawing
  • US20250311289A1 patent drawing
  • US20250311289A1 patent drawing

AI summary

A semiconductor device includes: a first electrode; a semiconductor layer provided on the first electrode; a second electrode provided on the semiconductor layer; a control electrode provided in the semiconductor layer via an insulating region; a first conductive portion facing the control electrode, electrically connected to the second electrode, and having a first work function; a first semiconductor region of a first conductivity type provided in the semiconductor layer, sandwiched between the insulating region and the first conductive portion, and forming a Schottky junction with the first conductive portion; a second semiconductor region of a first conductivity type provided in the semiconductor layer, located on the first semiconductor region, and having an impurity concentration higher than the first semiconductor region; and a second conductive portion electrically connected to the second electrode, having a second work function, and forming an ohmic junction with the second semiconductor region.