Heterostructure Transistor Gate Stack for Diffusion-Limited Leakage
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Solution Overview
Problem
Highly-scaled transistors, particularly those using Gallium Nitride and other compound semiconductors, are susceptible to leakage and breakdown due to issues like atomic diffusion and poor metal coverage during fabrication, leading to reduced performance and premature failure.
Innovation Solution
A transistor design featuring a semiconductor heterostructure with a two-dimensional electron gas (2DEG) and a metal layer that forms a Schottky contact, along with a thicker metal gate electrode, is implemented. This design includes a thin metal layer to impede atomic diffusion from the gate electrode and a conformal metal layer to prevent unwanted metal diffusion, ensuring effective surface passivation and improved device reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a metal gate electrode is used in highly-scaled transistors, then power handling capabilities and switching speeds are improved, but atomic diffusion from the gate electrode to the channel region causes leakage and breakdown
Solution Approach 1:
A thin metal layer is introduced as an intermediary between the metal gate electrode and the channel region. This intermediate layer acts as a diffusion barrier that prevents atomic diffusion from the gate electrode to the channel, thereby reducing leakage and breakdown while maintaining the electrical performance benefits of the metal gate electrode.
Solution Approach 2:
The gate structure is designed as a composite material system consisting of multiple layers: a metal gate electrode layer, a thin metal barrier layer, and an electrically insulating material layer. This composite structure combines the high conductivity of metal with the protective properties of barrier and insulating materials to achieve both high switching speed and improved reliability.
2Power
If metal layers are used to form gate electrodes in highly-scaled devices, then power handling capabilities are improved, but metal contamination and poor metal coverage during fabrication lead to leakage and breakdown
Solution Approach 1:
The thin metal layer serves as a mediator that ensures uniform metal coverage across the gate region. This intermediate layer provides a consistent foundation that improves metal coverage uniformity during fabrication, preventing the leakage and breakdown caused by poor coverage while preserving the high power handling capabilities of the metal gate structure.
Solution Approach 2:
The thin metal layer is deposited in advance before forming the final gate electrode structure. This preliminary action ensures that the underlying surface has uniform metal coverage, which prevents subsequent fabrication issues and ensures consistent device performance across the wafer.
3Reliability
If the gate electrode is made thinner to reduce diffusion, then atomic diffusion is reduced, but electrical conductivity and power handling capabilities deteriorate
Solution Approach 1:
The gate structure is segmented into functionally distinct layers: a thick metal gate electrode layer for high conductivity and power handling, and a thin metal barrier layer for preventing atomic diffusion. This segmentation allows each layer to be optimized for its specific function, maintaining both low diffusion and high electrical performance.
Solution Approach 2:
Different layers of the gate structure have different thicknesses and properties optimized for local functions. The metal gate electrode layer is thick to provide high conductivity and power handling, while the thin metal barrier layer is thin to prevent diffusion. This local quality differentiation resolves the contradiction between diffusion resistance and electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the reliability and performance of transistors by reducing atomic diffusion and metal contamination, thereby improving switching speeds and power handling capabilities while maintaining acceptable thermal performance.
Implementation Method 1
The first metal layer forms a Schottky contact to the channel region
Implementation Method 2
The first metal layer is configured to impede atomic diffusion from the metal gate electrode to the channel region
Implementation Method 3
a metal gate electrode having a second thickness that is greater than the first thickness disposed above the first metal layer that forms an Ohmic contact to the first metal layer
Data Source
Figure 1A
Figure 1B
Figure 2
AI summary
A heterostructure-based high electron mobility transistor includes a channel region in which a two-dimensional electron gas is formed which is protected by insulating material. A control terminal contacts the channel region within an aperture in the insulating material. The control terminal includes a first metal layer that forms a Schottky contact to the channel region within the aperture and a gate electrode which overlies the first metal layer and the channel region and extends above the channel region adjacent to the aperture.