Schottky Gate Stack Thickness for Low-Diffusion GaN Transistors
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Solution Overview
Problem
Existing semiconductor devices face issues with metal atom diffusion during thermal processing, leading to decreased Schottky barrier height and increased on-resistance due to current collapse, which are not adequately addressed by existing layer thickness definitions for gate electrode components.
Innovation Solution
A semiconductor device design incorporating a gate electrode with specific layer thicknesses for TaN and TiN layers, oriented in the (111) plane, forming an NaCl structure, to minimize metal atom diffusion and enhance reliability and reduce on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional semiconductor manufacturing processes are used, then existing device performance is maintained, but transistor density and switching speed cannot be further improved
Solution Approach 1:
The patent changes the physical and chemical parameters of the gate electrode structure by forming a multi-layer stack (TiN/HfO2/SiO2/HfO2/TiN) with specific thicknesses and properties. This parameter change enables higher transistor density while maintaining reliable electrical characteristics through controlled dielectric constants and interface properties.
Solution Approach 2:
The patent employs composite materials in the gate electrode structure, combining multiple dielectric layers (HfO2 with different dielectric constants, SiO2) and metal layers (TiN). This composite approach allows optimization of both transistor density and electrical performance by leveraging the complementary properties of each material.
2Productivity
If gate electrode width is reduced to increase density, then transistor density improves, but manufacturing precision requirements increase
Solution Approach 1:
The gate electrode is segmented into multiple functional layers (TiN bottom electrode, HfO2/SiO2/HfO2 dielectric stack, TiN top electrode) that can be independently formed and controlled. This segmentation allows each layer to be optimized for its specific function while maintaining overall dimensional control through sequential processing steps.
Solution Approach 2:
Different regions of the gate structure have different local properties: the bottom TiN layer provides adhesion and electrical contact, the HfO2/SiO2/HfO2 stack provides dielectric function with controlled breakdown characteristics, and the top TiN layer provides planarity and electrical contact. This local quality optimization enables precise dimensional control at each interface.
3Speed
If conventional gate electrode structures are used, then manufacturing process is simple, but field effect mobility and switching speed are insufficient
Solution Approach 1:
The patent optimizes the dielectric constant profile through the gate stack by using HfO2 layers with different dielectric constants (4.0 and 20.0) in specific positions. This parameter optimization enhances the electric field distribution, improving carrier mobility and switching speed while managing the increased structural complexity.
Solution Approach 2:
The patent replaces conventional single-material gate dielectrics with a multi-layer dielectric stack that uses electrical field distribution optimization instead of relying solely on mechanical dimensional scaling. This substitution enables improved switching speed through enhanced electric field control rather than just reducing physical dimensions.
Data Source
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AI summary
A semiconductor device (100A) includes: a first nitride semiconductor layer (103); a second nitride semiconductor layer (104); a source electrode (301) and a drain electrode (302); and a gate electrode (401) that is spaced apart from the source electrode (301) and the drain electrode (302), and is in contact with the second nitride semiconductor layer (104). The gate electrode (401) includes: a first barrier layer (401a) that includes TaN, has a layer thickness of Z1, and forms a Schottky junction with the second nitride semiconductor layer (104); a second barrier layer (401b) that is disposed above and in contact with the first barrier layer (401a), includes TiN or WN, and has a layer thickness of Z2; and a wiring layer disposed above and in contact with the second barrier layer (401b). In the semiconductor device (100A), 200 nm ≥ Z1+Z2 ≥ 50 nm, Z1 < Z2, and 50 nm > Z1 > 3 nm are satisfied.