Schottky-Gated Germanium Channel for Cryogenic Threshold Stability
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Solution Overview
Problem
Existing semiconductor devices face challenges in operating efficiently at cryogenic temperatures due to instabilities and shifts in threshold operation voltage caused by undesirable charges at the interface between the gate dielectric and semiconductor, which can deteriorate doped contact regions.
Innovation Solution
The use of a Schottky gate and undoped gate structures in a semiconductor device with a compressively-strained germanium layer, eliminating the need for doped contact regions and reducing undesirable charges, thereby stabilizing operation at cryogenic temperatures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a MOS- or MIS-type gate with gate dielectric is used, then the device structure is conventional and easier to manufacture, but undesirable charges accumulate at the interface between gate dielectric and semiconductor causing instabilities and shifts in threshold operation voltage
Solution Approach 1:
The patent removes the gate dielectric layer entirely from the gate structure, eliminating the interface where undesirable charges accumulate. This extraction of the problematic dielectric component directly resolves the voltage instability issue while simplifying the overall device structure.
Solution Approach 2:
The invention changes the fundamental parameter of the gate structure by transitioning from a dielectric-based gate (MOS/MIS) to a direct metal-semiconductor Schottky gate. This parameter change eliminates charge accumulation at the interface and stabilizes threshold voltage operation.
2Reliability
If doped contact regions are used, then the device can operate at room temperature with adequate carrier concentration, but the doped regions deteriorate at cryogenic temperatures due to carrier freezeout
Solution Approach 1:
The patent changes the operational parameter of carrier concentration by using undoped semiconductor material with high intrinsic carrier concentration at cryogenic temperatures, replacing the temperature-dependent doped contact regions. This eliminates carrier freezeout effects while maintaining manufacturability through simplified fabrication processes.
3Loss of energy
If conventional semiconductor devices are used at cryogenic temperatures, then the device structure is simple, but power dissipation increases and performance deteriorates due to material properties at low temperatures
Solution Approach 1:
The patent employs a composite material system consisting of undoped semiconducting material with specific crystal orientation combined with a Schottky gate structure. This composite approach optimizes both power dissipation and performance at cryogenic temperatures by leveraging the unique properties of the material combination rather than using conventional single-material structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The semiconductor device achieves high hole mobility, ultra-low power dissipation, and stable performance at cryogenic temperatures, suitable for applications in quantum computing and cryogenic electronics.
Implementation Method 1
a Schottky junction is formed between the metal gate and the semiconductor structure
Implementation Method 2
compressively strained germanium grown on silicon (cs-GoS)
Implementation Method 3
holes having a record-high mobility (4.3×106 cm2V−1S−1) in the compressively strained germanium
Data Source
AI summary
A semiconductor device (1) is disclosed. The semiconductor device (1) comprise a substrate (2), a semiconductor structure (4) disposed on the substrate, having a principal surface (5), and comprising a semiconductor layer (10) running between first and second ends (12, 13); and a metal gate (30) disposed on the principal surface of the semiconductor structure such that a Schottky junction (31) is formed between the metal gate and the semiconductor structure, wherein the metal gate is disposed over a section (19) of the semiconductor layer between the first and second ends of the semiconductor layer for forming a channel in the semiconductor layer and controlling conduction of charge carriers between the first and second ends of the semiconductor layer.