Self-Aligned Schottky Junction Fabrication via SiGe Etching
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Solution Overview
Problem
Conventional methods for forming Schottky junctions in semiconductor devices face challenges such as increased access resistance and difficulty in achieving well-defined, abrupt junctions due to scattering and diffusion issues during impurity implantation and annealing, especially as device dimensions shrink, and silicidation processes can lead to unwanted diffusion affecting junction shape and position.
Innovation Solution
A method involving selective deposition and etching to create a self-aligned metal-semiconductor junction by forming a sacrificial SiGe layer, etching a recess, and filling it with metal through a contact hole, allowing for precise control over junction geometry and placement, eliminating the need for silicidation and reducing resistivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If impurity implantation and annealing are used to form junctions, then junction depth can be controlled, but access resistance increases and junction definition becomes poor due to scattering and diffusion
Solution Approach 1:
The patent replaces the conventional impurity implantation and annealing process with a metal deposition process to form Schottky junctions. This substitution eliminates the scattering and diffusion issues inherent in thermal processes, achieving both low access resistance and well-defined junction profiles through direct metal deposition onto the semiconductor surface.
Solution Approach 2:
The patent changes the fundamental approach from modifying the semiconductor substrate (impurity implantation) to depositing a metal layer (Schottky contact). This parameter change transforms the junction formation mechanism, allowing precise control of junction depth and profile through deposition parameters while inherently achieving low resistance contact.
2Ease of manufacture
If silicidation process is used to form Schottky junctions, then selectivity is improved, but unwanted diffusion occurs during metal-silicon reaction affecting junction shape and position
Solution Approach 1:
The patent extracts the problematic metal-silicon reaction step from the junction formation process. By depositing metal directly onto the semiconductor surface without forming an intermediate silicide layer, the method eliminates unwanted diffusion phenomena while maintaining selectivity through controlled deposition conditions and material selection.
Solution Approach 2:
The patent introduces a carefully controlled deposition process as an intermediary between metal application and semiconductor contact. This intermediary step allows precise control of the metal-semiconductor interface formation, preventing uncontrolled diffusion while maintaining the benefits of selective metal deposition.
3Manufacturing precision
If metal deposition is used to form Schottky junctions, then junction shape and position control is improved, but metal may be deposited on unwanted areas causing short circuits
Solution Approach 1:
The patent performs preliminary patterning and preparation steps before metal deposition to define the exact areas where metal should be deposited. By pre-defining the junction regions through selective surface preparation or masking, the method ensures metal is deposited only where intended, eliminating short circuit risks while maintaining precise shape and position control.
Solution Approach 2:
The patent employs self-aligned deposition techniques where the metal deposition process itself is guided by the substrate features or previously deposited layers. The metal automatically deposits only on the intended semiconductor regions due to the self-aligning nature of the process, eliminating the need for additional masking steps and preventing short circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of self-aligned metal-semiconductor junctions with improved shape and depth control, reducing resistivity and minimizing the risk of short circuits, while allowing for the use of different metals for pMOS and nMOS devices with varying junction thicknesses.
Implementation Method 1
selectively etching said dielectric material at said junction region to form a contact hole; subsequently removing said sacrificial material from said recess to create a cavity
Implementation Method 2
filling said cavity with a metallic material via said contact hole
Data Source
AI summary
A method of fabricating a self-aligned Schottky junction (29) in respect of a semiconductor device. After gate etching and spacer formation, a recess defining the junction regions is formed in the Silicon substrate (10) and a SiGe layer (22) is selectively grown therein. A dielectric layer (24) is then provided over the gate (14) and the SiGe layer (22), a contact etch is performed to form contact holes (26) and the SiGe material (22) is then removed to create cavities (28) in the junction regions. Finally the cavities (28) are filled with metal to form the junction (29). Thus, a process is provided for self-aligned fabrication of a Schottky junction having relatively low resistivity, wherein the shape and position of the junction can be well controlled.