Integrated Schottky-PN Diode Cell Layout for Lower Conduction Loss
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing semiconductor device structure with separate Schottky cell and p-n diode cells leads to scattered current paths, resulting in inadequate increase in forward current with increasing forward voltage, thereby failing to reduce conduction loss effectively in Schottky barrier diodes.
Innovation Solution
A semiconductor device design where a Schottky junction and an ohmic junction are formed within a single unit cell in the semiconductor layer, allowing current paths for both the Schottky barrier diode and the transistor to be concentrated directly below the unit cell, thereby enhancing the increase in forward current with respect to forward voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If Schottky cell and p-n diode cell are formed separately, then device structure is simplified and manufacturing is easier, but current paths become scattered and conduction loss increases
Solution Approach 1:
The patent merges the Schottky cell and p-n diode cell into a single integrated cell structure. The Schottky barrier diode and the transistor share common regions (n-type drift region, n-type buffer region, p-type substrate) within the same cell, consolidating what were previously separate current paths into a unified structure. This merging eliminates the scattering effect while maintaining manufacturability through standard semiconductor fabrication processes.
2Device complexity
If separate Schottky cell and p-n diode cell structure is used, then device design is simpler, but forward current increase rate with forward voltage is insufficient
Solution Approach 1:
The integrated cell structure combines the Schottky barrier diode formation region and transistor formation region within the same cell boundaries. The Schottky barrier diode current path and transistor current path converge through shared doped regions, creating a unified current flow that enhances the forward current increase rate while maintaining reasonable device design complexity.
Solution Approach 2:
The single cell structure serves multiple functions: it forms both the Schottky barrier diode and the transistor with shared regions. The n-type drift region and n-type buffer region serve as common elements for both device types, allowing the structure to achieve enhanced power characteristics through multi-functionality without proportionally increasing design complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces conduction loss in Schottky barrier diodes by concentrating current paths, improving the rate of increase in forward current with respect to forward voltage.
Implementation Method 1
a gate electrode layer facing the well region and the first conductivity type region through a gate insulating layer and a first main surface electrode covering the diode region and the first conductivity type region on the first main surface of the semiconductor layer, and forming a Schottky junction with the diode region
Implementation Method 2
forming a Schottky junction with the diode region and an ohmic junction with the first conductivity type region
Data Source
AI summary
A semiconductor device includes a semiconductor layer having a first main surface on one side and a second main surface on the other side, a unit cell including a diode region of a first conductivity type formed in a surface layer portion of the first main surface of the semiconductor layer, a well region of a second conductivity type formed in the surface layer portion of the first main surface of the semiconductor layer along a peripheral edge of the diode region, and a first conductivity type region formed in a surface layer portion of the well region, a gate electrode layer facing the well region and the first conductivity type region through a gate insulating layer and a first main surface electrode covering the diode region and the first conductivity type region on the first main surface of the semiconductor layer, and forming a Schottky junction with the diode region and an ohmic junction with the first conductivity type region.