Integrated Schottky Diode Test Structure for Low-Current Surge Screening
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Solution Overview
Problem
Testing the surge current capability of high-power silicon carbide Schottky diodes is challenging due to the high currents required, which are difficult to generate and measure, especially at the wafer sort level and after packaging, leading to variability in device performance and limited ability to guarantee maximum surge current specifications.
Innovation Solution
Incorporating an integrated test structure within the semiconductor device that allows for the application of a lower current to an anode test pad to evaluate surge performance, enabling in-situ testing and correlation of surge current capability across individual dies on a wafer, rather than relying on a single process control monitoring die.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high current is applied to test surge current capability, then accurate surge performance evaluation is achieved, but testing becomes difficult and variable due to high current generation and measurement challenges
Solution Approach 1:
The device is segmented into a main active area and a separate test area within the same die. The test area includes a test anode contact and test cathode contact that can be independently accessed. This segmentation allows surge current testing to be performed on a dedicated test region without requiring high current through the entire device, reducing measurement difficulty and variability while maintaining evaluation accuracy.
Solution Approach 2:
The test area acts as an intermediary structure that mediates between the need for accurate surge current evaluation and the difficulty of high current measurement. By providing a dedicated test path with separate contacts, the test area enables indirect measurement of surge capability through lower current application, avoiding the direct high current measurement problems.
2Device complexity
If testing is performed on a single process control monitoring die, then manufacturing complexity is reduced, but the ability to guarantee maximum surge current specifications across all devices is limited
Solution Approach 1:
The test area is merged with the main active area on the same die, combining testing functionality with the operational device structure. This integration allows surge current capability to be evaluated on every individual die during manufacturing, ensuring that each device meets specifications while maintaining a unified structure that doesn't significantly increase overall device complexity.
Solution Approach 2:
The test area provides universal testing capability across all devices on a wafer. Each die contains its own test contacts and test area, enabling standardized surge current evaluation on every device rather than relying on separate process control monitoring. This multi-functional design ensures consistent specification guarantee across the entire production batch.
3Reliability
If integrated test structure is incorporated within each device, then surge capability evaluation for each die is enabled, but device structure complexity increases
Solution Approach 1:
The test area is implemented with local quality by concentrating testing functionality in a specific region of the die rather than distributing it throughout. The test anode contact, test cathode contact, and associated structures are localized to a defined test area, allowing surge capability evaluation while minimizing the impact on the overall device structure and maintaining clean separation between test and operational regions.
Data Source
AI summary
A semiconductor device includes a semiconductor layer having a first area and an edge termination area outside the first area. The semiconductor layer has a first conductivity type, an active area in the first area, a test area in the first area adjacent the active area, a first anode contact on the semiconductor layer in the active area, a second anode contact on the semiconductor layer in the test area, and a cathode contact in electrical contact with the semiconductor layer. A related method of testing surge current capability of a semiconductor device includes applying a forward current that is smaller than a maximum forward current of the semiconductor device to a test active area that is within an area inside a main edge termination area of the semiconductor device, and detecting a failure of the semiconductor device in response to the forward current.