Schottky Barrier Transistor Fabrication via Self-Aligned Metal Gate
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Solution Overview
Problem
The short channel effect in transistors with gate lengths of 50 nm or less leads to reduced channel controllability and electrical characteristics, and existing methods like channel doping and gate dielectric thinning face limitations such as random doping and gate leakage, while aligning errors during source and drain formation exacerbate scaling issues.
Innovation Solution
A method for fabricating a Schottky barrier transistor using two perpendicular masking processes, where a metal gate is formed after creating source and drain regions, and a Schottky barrier is formed at low temperatures by annealing the substrate, increasing the contact area between the channel and gate, and using high-k materials for reduced leakage and low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If channel doping method is used to address short channel effect, then channel controllability is improved, but random doping problem occurs
Solution Approach 1:
The patent removes the doping step entirely from the fabrication process. Instead of doping the channel to improve controllability, the invention uses a fully depleted body structure where the channel is intrinsic or lightly-doped, and achieves short channel effect control through the combination of thin body thickness and high-k gate dielectric, thereby eliminating random doping issues while maintaining channel controllability.
Solution Approach 2:
The patent changes the key parameter from channel doping concentration to body thickness and gate dielectric properties. By reducing body thickness to a few nanometers and using high-k gate dielectric materials, the invention achieves better electrostatic control without requiring precise doping, thus resolving the contradiction between channel controllability and manufacturing precision.
2Reliability
If gate dielectric thinning method is used to address short channel effect, then channel controllability is improved, but gate leakage increases
Solution Approach 1:
The patent changes the gate dielectric parameter from thin silicon oxide to high-k materials with dielectric constants significantly higher than silicon oxide. This allows maintaining a thicker physical thickness (reducing leakage) while achieving equivalent or better electrical thickness (improving controllability), thus resolving the contradiction between channel controllability and gate leakage.
Solution Approach 2:
The patent employs composite gate stack structures combining high-k gate dielectric materials with metal gate electrodes. This composite structure provides both the high dielectric constant needed for strong electrostatic control and the appropriate work function to prevent gate leakage, simultaneously achieving improved channel controllability and reduced gate leakage.
3Ease of manufacture
If multiple mask processes are used to form source and drain after channel, then fabrication flexibility is improved, but aligning errors increase
Solution Approach 1:
The patent performs source and drain formation before channel patterning. By forming source and drain regions first using self-aligned processes, and then defining the channel through subsequent patterning steps, the invention eliminates alignment errors between these critical regions while maintaining fabrication flexibility through the sequential process design.
Solution Approach 2:
The patent employs self-aligned fabrication processes where previously formed structures serve as alignment references for subsequent steps. The source and drain regions formed in earlier steps automatically provide the alignment reference for channel patterning, eliminating the need for separate alignment operations and their associated errors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively addresses aligning errors, reduces power consumption, and enhances switching speed by forming a metal gate with a Schottky barrier, improving channel controllability and electrical characteristics in transistors with short channels.
Implementation Method 1
a gate dielectric layer and a gate electrode are sequentially formed on three surfaces of the channel in the lengthwise direction
Implementation Method 2
one of the operations (b) through (e) further comprises forming a Schottky barrier by annealing the substrate. The annealing may be performed at a temperature of 450 to 600° C.
Implementation Method 3
forming a Schottky barrier between a source and drain, and the channel
Data Source
AI summary
Provided is a method of fabricating a Schottky barrier transistor. The method includes (a) forming a pair of cavities for forming a source forming portion and a drain forming portion having a predetermined depth and parallel to each other and a channel forming portion having a fin shape between the cavities in a substrate;(b) filling the pair of cavities with a metal; (c) forming a channel, a source, and a drain by patterning the channel forming portion, the source forming portion, and the drain forming portion in a direction perpendicular to a lengthwise direction of the channel forming portion; (d) sequentially forming a gate oxide layer and a gate metal layer that cover the channel, the source, and the drain on the substrate; and (e) forming a gate electrode corresponding to the channel by patterning the gate metal layer, wherein one of the operations (b) through (e) further comprises forming a Schottky barrier by annealing the substrate.