Integrated Schottky Trench Structure for Low-Inductance MOSFET Rectification

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Solution Overview

Problem

The integration of Schottky diodes with MOSFETs in parallel circuits leads to increased parasitic inductance, reducing performance and increasing costs due to the external connection, which is not optimal for low power consumption and high switching speed applications.

Innovation Solution

A semiconductor structure incorporating a Schottky diode with a first N-type semiconductor layer, trench, insulating layer, polysilicon or metal silicide layers, and a grounded P-type protective layer, where the polysilicon or metal silicide layers are disposed in parallel and the metal layer forms electrodes, creating a Schottky junction and an electron accumulated region to enhance forward current and reduce parasitic inductance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the Schottky diode is externally connected to the MOSFET device in parallel, then the rectifier function is achieved, but the parasitic inductance is increased and performance decreases

Engineering Contradiction:
Improverectifier functionVSAvoidparasitic inductance
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent merges the Schottky diode and MOSFET into a single integrated device structure. The Schottky diode is formed by creating a metal-semiconductor junction at the top surface of the N-type semiconductor layer, while the MOSFET is formed within the same semiconductor substrate. This integration eliminates the need for external connections between separate components, thereby reducing parasitic inductance while maintaining the rectifier function.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The integrated device structure serves multiple functions: the N-type semiconductor layer with metal contact forms both the anode of the Schottky diode and the source/drain region of the MOSFET, while the P-type protective layer provides both diode cathode functionality and MOSFET gate isolation. This multi-functionality reduces the need for additional components and external connections.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If the Schottky diode is externally connected to the MOSFET device in parallel, then the rectifier function is achieved, but the cost increases

Engineering Contradiction:
Improverectifier functionVSAvoidcost
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines two separate devices (Schottky diode and MOSFET) into a single integrated structure, reducing component count and assembly complexity. The shared semiconductor substrate and overlapping fabrication processes lower manufacturing costs compared to external connections requiring additional packaging and interconnects.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If the Schottky junction gap is increased to enhance forward current value, then the conductivity is improved, but the device area increases

Engineering Contradiction:
Improveforward current valueVSAvoiddevice area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent employs localized doping regions with varying concentrations to optimize current distribution. The P-type protective layer has a doping concentration higher than the N-type semiconductor layer, creating localized high-field regions that enhance forward current without requiring proportional increases in overall device area. The trench structure also concentrates the electric field in specific regions.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent introduces a vertical dimension through the trench structure extending into the semiconductor layer. This three-dimensional configuration allows the Schottky junction gap to be optimized in the vertical direction while maintaining a compact planar footprint, effectively decoupling the forward current enhancement from lateral area expansion.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed structure increases forward current values and reduces parasitic inductance, improving the performance and efficiency of the Schottky diode by forming a Schottky junction and electron accumulated region, while maintaining low power consumption and high switching speed.

Implementation Method 1

a Schottky junction is formed at a junction of the metal layer and a top of the first N-type semiconductor layer

Methodology Applied
Scientific EffectSchottky junction:

Implementation Method 2

An electron accumulated region is formed outside the first insulating layer

Methodology Applied
Scientific EffectElectron accumulation:

Implementation Method 3

An interface between a bottom surface of the first P-type protective layer and the first N-type semiconductor layer has a PN junction

Methodology Applied
Scientific EffectPN junction:

Data Source

PatentUS20230275161A1Semiconductor structure
Publication Date: 2023.08.31 HEXIC SEMICONDUCTOR INC
  • US20230275161A1 patent drawing
  • US20230275161A1 patent drawing
  • US20230275161A1 patent drawing

AI summary

A semiconductor structure includes a Schottky diode structure, which includes: a first trench extending through a first N-type semiconductor layer and being disposed in the first N-type semiconductor layer; a first insulating layer disposed in the first trench; two polysilicon layers or metal silicide layers disposed in the first trench, wherein an upper one and a lower one of the polysilicon layers or metal silicide layers are disposed in parallel; a first P-type protective layer, which is grounded and disposed on a bottom of the first trench, and contacts the first insulating layer and a bottom surface of the lower one of the polysilicon layers or metal silicide layers; a metal layer respectively disposed as a top surface and a lower bottom surface of the semiconductor structure to form a source and a drain as electrodes for the semiconductor structure to be connected to an external device.