SCL Decoder Buffer Updates for Low-Latency Path Sorting

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Solution Overview

Problem

Current Polar Code Successive Cancellation List (SCL) decoders face inefficiencies due to high latency in data exchange between processor stages, which affects their operational complexity and bit error performance, especially at longer block sizes.

Innovation Solution

The proposed solution involves selective replacement and deferred update techniques in buffer management, where only changed LLR statistics are updated, and in-place calculation of bit estimates are performed, reducing the need for extensive data copying and sorting, thereby minimizing latency and improving computational efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional buffer management updates entire rows based on path metrics, then path metric accuracy is maintained, but data transfer overhead and latency increase significantly

Engineering Contradiction:
Improvepath metric accuracyVSAvoiddata transfer latency
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent extracts and updates only the changed LLR statistics portions rather than entire rows. The buffer management identifies and updates only the specific statistics that have changed since the previous update cycle, removing the unnecessary data transfer overhead of copying entire rows while maintaining path metric accuracy.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent segments the buffer update operation into selective portions. Instead of treating each row as an indivisible unit that must be copied entirely, the update mechanism is segmented to modify only the specific LLR statistics that have changed, reducing data transfer latency while preserving accuracy.

Inventive Principle:
Principle #1Segmentation

2Productivity

If in-place calculation is used for bit estimate updates, then data copying overhead is reduced, but buffer management complexity increases

Engineering Contradiction:
Improvecomputational efficiencyVSAvoidbuffer management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent inverts the conventional approach by performing in-place calculation of bit estimate updates directly in the buffer rather than calculating updates separately and then copying data. This reversal eliminates the need for extensive data copying and intermediate buffers, improving computational efficiency while the structured in-place update mechanism manages the complexity.

Inventive Principle:
Principle #13The other way round (Inversion)

3Measurement precision

If extensive sorting and data copying is performed, then path metric accuracy is maintained, but processing bottlenecks increase

Engineering Contradiction:
Improvepath metric accuracyVSAvoidprocessing throughput
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent extracts only the necessary path metric information that has changed and updates only those specific portions in the buffer. This selective extraction and update approach maintains path metric accuracy while eliminating the processing bottlenecks associated with sorting and copying entire rows of data.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS9973301B2Memory management and path sort techniques in a polar code successive cancellation list decoder
Publication Date: 2018.05.15 HYPERX HOLDINGS LLC
  • US9973301B2 patent drawing
  • US9973301B2 patent drawing
  • US9973301B2 patent drawing

AI summary

Various embodiments are described of a system and method for improved SCL decoder operation. In particular, various embodiments are described which improve the efficiency of the buffer management based on updated path metric statistics. In some embodiments, the SCL decoder may perform selective replacement to limit the extent of LLR updates per row only to the statistics that have changed since the previous update cycle. In some embodiments, the SCL decoder may perform deferred updates, which may involves in-place calculation of both ûφ=0 and ûφ=1 bit estimate (LLR) updates based on the row from which the updated row will be derived.