SCL Decoder Path Pruning With Sorted Index Copying

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Solution Overview

Problem

Existing SCL polar code decoders face high hardware complexity due to the large number of multiplexers required for copying operations in path pruning stages, which increases the overall complexity of the decoder architecture.

Innovation Solution

The proposed solution reduces the number of multiplexers by selecting the L paths with the smallest path metrics and sorting their indexes, allowing for the use of (L/2+1)-to-1 multiplexers instead of L-to-1 multiplexers for copying operations, thereby reducing hardware complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If L-to-1 multiplexers are used for copying operations in path pruning stages, then all L paths can be copied correctly, but hardware complexity increases significantly

Engineering Contradiction:

Improvepath copying correctnessVSAvoiddecoder hardware complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the path copying operation into two distinct phases: (1) sorting path metrics to establish a deterministic ordering of paths, and (2) copying only from parent paths to child paths based on this ordering. This segmentation eliminates the need for complex L-to-1 multiplexers by breaking down the copying task into simpler, ordered operations that can be performed with fewer resources.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary sorting of path metrics before the copying operation. By pre-establishing the sorted order of paths, the system determines in advance which paths are parents and which are children, eliminating the need for complex runtime multiplexing decisions. This preliminary action simplifies the subsequent copying phase significantly.

Inventive Principle:

Principle #10Preliminary action

2Device complexity

If sorting of path indexes is performed before copying, then the number of multiplexers is reduced, but additional processing steps are required

Engineering Contradiction:

Improvenumber of multiplexersVSAvoiddecoding latency

Core Design Contradiction:

Device complexityVSLoss of time

Solution Approach 1:

The patent merges the sorting operation with the existing path metric calculation and comparison logic that already occurs during SCL decoding. The sort is performed as part of the natural flow of path metric updates, combining what would otherwise be separate operations. This integration minimizes the time penalty of sorting while achieving the complexity reduction benefit.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The sorting operation is performed continuously alongside path metric calculations rather than as a separate batch operation. As path metrics are updated during decoding, the sorting structure is maintained and updated incrementally, ensuring that the useful action of path evaluation continues without interruption while the sorting benefit is realized.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS11374593B2Hardware complexity reduction technique for successive cancellation list decoders

Publication Date: 2022.06.28 ASELSAN ELEKTRONIK SANAYI & TICARET ANONIM SIRKETI

AI summary

A hardware complexity reduction method for successive cancellation list decoders (SCL) is provided. In path pruning stages of an SCL decoding, L paths with smallest path metrics out of 2L candidate paths are chosen as surviving candidate paths as in a conventional SCL algorithm. Moreover, path indexes of L surviving candidate paths are provided in a sorted manner according to indexes at an output of a sorter module. After a path pruning, instead of L-to-1 multiplexers, (L/2+1)-to-1 multiplexers are deployed to perform copying operations of any required elements stored in dedicated registers of the L surviving candidate paths.