SCM Memory Controller Dual-Area Write Mode Selection
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Solution Overview
Problem
Storage Class Memory (SCM) systems face performance issues with long latency during random write operations due to non-contiguous data writing based on CPU-designated addresses, necessitating improved write performance.
Innovation Solution
The SCM system employs a dual-memory area architecture, using In-Place Update for the first memory area and Append Write for the second memory area, allowing dynamic selection of the write method based on internal controller states and memory conditions, thereby avoiding the need for time-consuming Read Modify Write processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If In-Place Update is used for all write operations, then write latency is reduced, but data consistency and reliability deteriorate due to inability to handle concurrent modifications
Solution Approach 1:
The memory space is segmented into two distinct areas: a volatile memory area for high-speed In-Place Update operations and a non-volatile memory area for reliable Append Write operations. This segmentation allows each area to serve its specific function optimally, resolving the contradiction between speed and reliability.
Solution Approach 2:
The system dynamically switches between In-Place Update and Append Write modes based on real-time detection of memory area states. When the volatile memory area is available and no concurrent modifications are detected, In-Place Update is used for speed; when conflicts are detected or non-volatile memory is needed, Append Write is used for reliability.
2Reliability
If Read Modify Write process is used to ensure data consistency, then data reliability is improved, but write performance deteriorates due to additional read operations
Solution Approach 1:
The system performs preliminary actions by establishing a volatile memory area that can be written to without immediate read-modify-write cycles. By pre-allocating this high-speed buffer area, the system avoids the need for time-consuming Read Modify Write processes while maintaining data consistency through controlled synchronization mechanisms.
Solution Approach 2:
The volatile memory area acts as an intermediary between the CPU and non-volatile memory. It receives write operations, maintains data consistency through its own memory model, and only performs Append Write to non-volatile memory when necessary, thereby eliminating the need for Read Modify Write cycles.
3Reliability
If Append Write is used for all write operations, then data consistency is maintained, but write latency increases due to sequential writing requirements
Solution Approach 1:
The memory system is segmented into two functional zones: a volatile memory zone optimized for low-latency In-Place Update operations and a non-volatile memory zone optimized for consistent Append Write operations. This segmentation enables the system to achieve both fast writes and data consistency by directing operations to appropriate zones.
4Productivity
If dual-memory area architecture is implemented, then write performance is improved through In-Place Update, but device complexity increases due to memory management overhead
Solution Approach 1:
The memory controller autonomously manages the dual-memory area architecture by self-determining when to use In-Place Update versus Append Write based on detected memory states and concurrent access patterns. This self-service approach eliminates the need for complex external memory management mechanisms while maintaining high write performance.
Data Source
AI summary
According to one embodiment, a memory system includes a non-volatile memory and a controller. The non-volatile memory includes first and second memory areas. The controller is configured to, when receiving a write command from the host, determine a write method. The controller is configured to, when a first method is determined, write the data to the first memory area. The controller is configured to, when a second method is determined, write the data to the second memory area. The first method is a write method of writing the data to a physical address associated with the logical address designated in the write command. The second method is a write method of writing the data to a physical address designated by the controller.