Storage Class Memory Dual Interface Read Write Optimization
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Solution Overview
Problem
Storage Class Memory (SCM) exhibits longer write latency compared to read latency, hindering its adoption as a cost-effective and power-efficient alternative to conventional memories like DRAM or SRAM due to the inefficiencies in handling byte-addressable data.
Innovation Solution
Implementing a dual-interface approach where read requests are handled through a memory device interface for byte-addressable data and write requests are aggregated and managed through a block device interface, reducing latency by buffering and flushing data in larger blocks, thereby leveraging the faster read capabilities of SCM while mitigating its write latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If SCM is used for byte-addressable data access, then read speed is improved, but write latency increases
Solution Approach 1:
The patent segments the interface into two distinct paths: a memory device interface for read operations and a block device interface for write operations. This segmentation allows each interface to be optimized for its specific function, enabling fast byte-addressable reads while handling writes through block operations that reduce latency
Solution Approach 2:
The patent introduces a dual-interface architecture that acts as an intermediary between the host and SCM. The memory device interface and block device interface work together to mediate read and write operations, allowing the system to leverage the strengths of both interfaces while mitigating their individual weaknesses
2Use of energy by moving object
If SCM is used as alternative to DRAM/SRAM, then power consumption and cost are reduced, but write performance deteriorates
Solution Approach 1:
The patent segments write operations into block-based transactions through the block device interface, which improves write performance by reducing the frequency of write operations to SCM. This segmentation approach maintains the power efficiency and cost benefits of SCM while addressing write performance limitations
Solution Approach 2:
The patent changes the operational parameters of write operations by transitioning from byte-addressable writes to block-based writes. This parameter change in the write operation structure improves write performance while maintaining the energy efficiency advantages of SCM
3Ease of operation
If byte-addressable access is implemented, then data accessibility is improved, but write operation efficiency decreases
Solution Approach 1:
The patent segments the access operations into two categories: byte-addressable reads through the memory device interface and block-based writes through the block device interface. This segmentation maintains full data accessibility for reads while improving write operation efficiency through block transactions
Solution Approach 2:
The patent inverts the conventional approach by making reads the primary byte-addressable operation while writes are handled through block operations. This inversion allows the system to maintain data accessibility for reads while improving write efficiency through the alternative block-based approach
Data Source
AI summary
A write request is received to write byte-addressable data corresponding to a first entry of a plurality of entries in a page table, and the byte-addressable data is written in a buffer of a host memory. A read request is received to read byte-addressable data corresponding to a second entry of the plurality of entries in the page table, and a read command is sent to a device using a memory device interface to read the byte-addressable data from a Storage Class Memory (SCM) of the device. According to another aspect, control circuitry of the device uses a block device interface for receiving commands from a host to read and write data in blocks in the SCM. The control circuitry also uses a memory device interface for receiving read commands from the host to read byte-addressable data from the SCM.