Storage Class Memory ECC Layout for Low-Latency DDR Reliability
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Solution Overview
Problem
Current storage class memories (SCM) face challenges in improving reliability and minimizing access latency while being compatible with the DDR protocol, due to uncertain access latency and low universality.
Innovation Solution
Implementing a two-level memory error correction mechanism with first-type and second-type memory chips, where the second-type chips store running error correction code for first-level correction and retry error correction code for second-level correction, ensuring high reliability and compatibility with the DDR protocol by arranging memory chips to meet the DDR bit width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a built-in controller with high-complexity error correction algorithm is used, then reliability is improved, but access latency increases
Solution Approach 1:
The error correction functionality is segmented into two distinct types: running error correction code stored in second-type memory chips for rapid first-level correction, and retry error correction code stored in first-type memory chips for second-level correction. This segmentation allows the system to perform quick error checks with minimal latency while maintaining comprehensive error correction capability for high reliability.
2Adaptability or versatility
If memory chips are arranged to meet DDR bit width, then universality is improved, but device complexity increases
Solution Approach 1:
The storage class memory is designed with memory chips arranged to meet standard DDR bit width requirements, enabling the device to interface with various processors using conventional DDR protocols. This universal design allows the SCM to function as a drop-in replacement or supplement to traditional DRAM, improving adaptability across different computing platforms while managing complexity through standardized interfaces.
Data Source
AI summary
A plurality of memory chips included in the storage class memory are divided into at least one group. Each group includes a first-type memory chip and a second-type memory chip. The second-type memory chip is configured to store running error correction code, and the first-type memory chip is configured to store data and retry error correction code. The running error correction code is for performing first-level memory error correction on the data stored in the first-type memory chip in the same group. The retry error correction code is for performing, when the first-level memory error correction fails, second-level memory error correction on the data stored in the first-type memory chip.