Storage-Class Memory Network Interface for Low-Latency Packet Handling
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Solution Overview
Problem
Traditional networked computing systems experience increased latency and CPU resource utilization due to round-trip communications and complex data preparation processes between processors, working memory, and network interface controllers (NICs), which are inefficient and resource-intensive.
Innovation Solution
A storage-class memory device integrating network, memory, and storage functions minimizes latency by allowing CPUs to perform network operations through onboard NICs, reducing the need for CPU interactions and offloading compute-intensive tasks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional separate NIC and processor architecture is used, then network communication functionality is achieved, but latency increases due to round-trip communications between processor, working memory, and NIC
Solution Approach 1:
The patent merges the NIC functionality directly into the storage-class memory device, eliminating the need for separate NIC and processor interactions. The storage-class memory device includes an integrated NIC that can directly transmit and receive network packets, while the processor accesses the memory device as if it were local memory, thereby eliminating round-trip communication latency between separate components.
Solution Approach 2:
The storage-class memory device serves multiple functions simultaneously: it provides high-capacity storage, acts as working memory for the processor, and includes integrated network interface capabilities. This multi-functionality eliminates the need for separate dedicated NIC hardware and reduces system complexity while improving performance.
2Use of energy by moving object
If processor directly manages network operations through working memory and NIC, then network communication is achieved, but CPU resource utilization increases due to complex data preparation and round-trip interactions
Solution Approach 1:
The storage-class memory device with integrated NIC performs network operations autonomously without requiring continuous processor intervention. The device can directly prepare and transmit network packets using its own resources, eliminating the need for the processor to repeatedly write data to working memory and issue DMA instructions, thereby reducing CPU resource utilization while maintaining high network operation efficiency.
3Speed
If data is stored in working memory for network transmission, then fast access is achieved, but data loss risk increases when working memory is cleared
Solution Approach 1:
The storage-class memory device combines the speed characteristics of volatile working memory with the persistence characteristics of non-volatile storage media. This composite memory architecture provides both fast data access speeds required for network operations and data persistence that prevents loss when memory is cleared, eliminating the trade-off between speed and reliability.
Data Source
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AI summary
Systems and techniques for storage-class memory device including a network interface are described herein. A write for a network communication is received by the host interface of the memory device. Here, the network communication includes a header. The header is written to a non-volatile storage array managed by a memory controller. A network command is detected by the memory device. Here, the network command includes a pointer to the header in the non-volatile storage array. The header is retrieved from the non-volatile storage array and a packet based on the header is transmitted via a network interface of the memory controller.