Memory Controller Selective ECC for SCM QoS and Tail Latency
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Solution Overview
Problem
Storage class memory (SCM) devices face challenges in maintaining quality of service (QoS) due to longer latency compared to DRAM, particularly during error correction and garbage collection, which degrades performance and increases latency.
Innovation Solution
A memory controller that performs selective and parallel error correction based on error correction options, including a variable error correction circuit and a fixed error correction circuit, to optimize latency and accuracy during data read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction is performed on all data read operations in SCM, then data reliability is improved, but latency increases and quality of service deteriorates
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the error correction level based on latency requirements. The memory controller receives latency requirements from the host and selectively applies different error correction levels (first level for high latency tolerance, second level for low latency tolerance) to different data blocks. This allows the system to maintain data reliability while optimizing latency performance by using minimal error correction where possible.
Solution Approach 2:
The patent implements dynamics by making the error correction process adaptive rather than static. The memory controller dynamically determines which data blocks require error correction and at what level, based on real-time latency requirements and error detection results. This dynamic approach allows the system to switch between aggressive error correction (when time permits) and minimal error correction (when latency is critical), resolving the contradiction between reliability and latency.
2Manufacturing precision
If high error correction level is applied to ensure data accuracy, then manufacturing precision is improved, but processing speed decreases
Solution Approach 1:
The patent applies partial action by selectively applying error correction only to data blocks that require it, rather than uniformly applying high-level error correction to all data. The memory controller first performs error detection on all read data, then applies error correction only to blocks that fail detection or have specific characteristics. This partial application of error correction maintains data accuracy where needed while preserving processing speed for data that doesn't require intensive correction.
Solution Approach 2:
The patent changes the error correction parameter (correction level) based on data characteristics and latency requirements. Instead of using a fixed high error correction level for all data, the system adjusts the correction level dynamically - using first error correction level for data with higher latency tolerance and second error correction level for time-critical data. This parameter adjustment resolves the contradiction between correction accuracy and processing speed.
Data Source
AI summary
A memory controller is provided that is configured to control a memory accessed by a device connected to a host processor via a bus. The memory controller is configured to control a memory accessed by a device connected to a host processor via a bus, and includes a first interface circuit configured to communicate with the host processor; a second interface circuit configured to communicate with the memory; an error detection circuit configured to detect an error present in data received from the second interface circuit in response to a first read request received from the first interface circuit; a variable error correction circuit configured to correct the error based on at least one of a reference latency and a reference error correction level included in a first error correction option; and a fixed error correction circuit configured to correct the error in parallel with an operation of the variable error correction circuit.