Storage Class Memory Wear Leveling via Write Cache and Address Rotation
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Solution Overview
Problem
Storage Class Memory (SCM) devices face challenges with finite write endurance, requiring effective wear leveling techniques to distribute writes evenly across memory locations, as existing table-mapping methods are inefficient due to SCM's byte-addressability and larger table size requirements.
Innovation Solution
A wear leveling technique combining cache filtering and address rotation, where data is written to a write cache and a designated nonvolatile memory location differently based on cache hits and misses, with address rotation redistributing writes over time and cache filtering providing short-term leveling, and error correction and metadata management ensuring data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If table-mapping wear leveling is used for SCM, then wear distribution can be achieved, but the table size becomes excessively large and access efficiency deteriorates due to SCM's byte-addressability
Solution Approach 1:
The patent segments the wear leveling function into two parts: a small mapping table for block-level wear leveling and a log structure for fine-grained wear distribution. The mapping table maps logical blocks to physical blocks, while the log records individual write operations with their target addresses. This segmentation allows the system to achieve comprehensive wear leveling without requiring a large table covering every byte address.
Solution Approach 2:
The patent introduces a temporal dimension by using a log structure that records write operations over time. Instead of maintaining a static large table, the system dynamically processes write requests through the log, distributing wear across different physical locations as writes occur. This transforms the wear leveling approach from a spatial table-lookup method to a temporal processing method.
2Productivity
If main memory capacity is increased to avoid disk access, then performance improves, but cost and power consumption increase
Solution Approach 1:
The patent applies local quality by implementing a write cache that selectively caches frequently written data blocks. Instead of increasing overall memory capacity, the system identifies and caches only the hot data that benefits from fast access. This allows performance improvement for critical operations while maintaining cost-effective and power-efficient storage for less frequently accessed data.
Solution Approach 2:
The patent uses partial action by implementing a write cache with limited capacity rather than full main memory expansion. The cache holds only the necessary portion of data that requires fast access, while other data remains in the cost-effective SCM. This partial caching approach delivers performance benefits for critical operations without the prohibitive cost and power consumption of fully expanding main memory.
3Productivity
If write cache is used for SCM, then write performance improves, but data loss risk increases during power loss
Solution Approach 1:
The patent applies preliminary action by implementing a log structure that records write operations before they are committed to the write cache. Each log entry contains the write data, target address, and sequence information. This preliminary logging ensures that if power is lost, the system can recover by replaying the log entries to reconstruct the write cache contents, thereby preventing data loss while maintaining write performance benefits.
Solution Approach 2:
The patent uses feedback mechanisms through sequence numbers and address tracking in the log structure. The system monitors write operations and maintains a record of which data has been cached and which has been persisted to SCM. This feedback information enables the system to recover accurately after power loss by knowing exactly what data needs to be restored to the write cache, balancing performance and reliability.
Data Source
AI summary
A method and apparatus of wear leveling control for storage class memory are disclosed. According to the present invention, whether current data to be written to a nonvolatile memory corresponds to a write cache hit is determined. If the current data to be written corresponds to the write cache hit, the current data are written to a write cache as well as to a designated location in the nonvolatile memory different from a destined location in the nonvolatile memory. If the current data to be written corresponds to a write cache miss, the current data are written to the destined location in the nonvolatile memory. If the current data to be written corresponds to the write cache miss and the write cache is not full, the current data is also written to the write cache. In another embodiment, the wear leveling control technique also includes address rotation process to achieve long-term wear leveling as well.