Storage-Class Memory Write Minimization via Trimmed State

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Computer systems face challenges in achieving high performance, low cost, and high endurance memory due to the limitations of Dynamic Random-Access Memory (DRAM) and Storage-Class Memory (SCM), where DRAM has low capacity and high cost, while SCM has limited write endurance.

Innovation Solution

Implementing techniques to minimize writes to each page or subpage of the SCM by tracking write operations, allocating unused pages with low write counts to new virtual machines, and marking de-allocated pages as 'trimmed' to reduce write operations, thereby balancing write distribution and extending the memory subsystem's endurance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If de-allocated memory pages are re-used without minimization writes, then memory allocation efficiency is improved, but write endurance of SCM is degraded

Engineering Contradiction:
Improvememory allocation efficiencyVSAvoidwrite endurance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by proactively identifying and marking memory pages as trimmed before they are fully de-allocated. This allows the system to prepare the pages for future reuse while minimizing write operations, thus resolving the contradiction between allocation efficiency and write endurance.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the state parameter of memory pages by introducing a 'trimmed' status that differs from traditional allocated/de-allocated states. This parameter change enables the system to reuse pages with minimal writes, simultaneously improving allocation efficiency and preserving write endurance.

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If traditional memory management is used without trimming, then implementation simplicity is maintained, but memory subsystem endurance is reduced

Engineering Contradiction:
Improveimplementation simplicityVSAvoidmemory subsystem endurance
Core Design Contradiction:
Device complexityVSDuration of action of stationary object

Solution Approach 1:

The patent segments the memory management process into distinct phases: allocation, trimming, and de-allocation. By introducing the trimming phase with minimal writes, the system extends memory endurance while maintaining relatively simple implementation through clear separation of concerns.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary 'trimmed' state between allocated and de-allocated states. This intermediary state acts as a buffer that allows pages to be prepared for reuse without requiring full de-allocation writes, thus extending endurance while keeping the management mechanism relatively simple.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If memory pages are fully de-allocated before reuse, then data security is improved, but write operations increase reducing SCM lifetime

Engineering Contradiction:
Improvedata securityVSAvoidSCM lifetime
Core Design Contradiction:
ReliabilityVSDuration of action of stationary object

Solution Approach 1:

The patent applies preliminary action by performing security-related trimming operations before full de-allocation. This allows the system to address security concerns early in the process while minimizing the number of write operations, thereby preserving SCM lifetime.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent applies partial action by performing minimal trim writes rather than full de-allocation writes. This partial action is sufficient to address security concerns for the trimmed portions while avoiding unnecessary writes to the entire page, thus extending SCM lifetime.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS10474359B1Write minimization for de-allocated memory
Publication Date: 2019.11.12 AMAZON TECH INC
  • US10474359B1 patent drawing
  • US10474359B1 patent drawing
  • US10474359B1 patent drawing

AI summary

Disclosed herein are techniques for reducing the number of write operations performed to a storage-class memory in a virtualized environment. In one embodiment, when a memory page is de-allocated from a virtual machine, the memory page and/or the subpages of the memory page are marked as “trimmed” in a control table such that any read to the memory page or subpages is denied, and no physical memory initialization is performed to the memory page or subpages. A de-allocated memory page or subpage is only initialized when it is reallocated and is to be written to by the virtual machine to which the memory page is reallocated.