Scoped Persistence Barriers for NVRAM Write Order
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Solution Overview
Problem
Non-volatile memory types used as a supplement or replacement for volatile RAM face issues with maintaining the order of write-back operations when power is interrupted and restored, leading to program errors due to out-of-order data persistence across multiple processors.
Innovation Solution
The implementation of scoped persistence barriers ensures that data from one set of instructions processed according to a hierarchical processing scope persists in NVRAM before data from another set of instructions, using a processing apparatus with NVRAM and processors configured to enforce this order, thereby preventing out-of-order write-backs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-volatile memory is used as main memory or primary storage, then data persistence when power is interrupted is improved, but data access time and cost increase
Solution Approach 1:
The memory system is segmented into multiple channels with separate write buffers, allowing parallel processing of write operations. Each channel maintains independent buffering capabilities, enabling simultaneous data persistence operations without blocking other channels, thus improving both reliability and access efficiency
Solution Approach 2:
Write buffers are introduced as intermediary structures between the memory interface and non-volatile memory cells. These buffers temporarily hold data during write operations, allowing the memory system to maintain high-speed access characteristics while ensuring data persistence to non-volatile storage, effectively mediating between speed and reliability requirements
2Productivity
If write operations are performed in parallel across multiple processors, then productivity is improved, but instruction order may be violated leading to program errors
Solution Approach 1:
The system performs preliminary actions by setting up dedicated write buffers and establishing write operation queues before parallel processing begins. Each processor channel is pre-configured with buffering resources, enabling parallel writes to proceed without compromising instruction order, as the structural framework for ordered persistence is already in place
Solution Approach 2:
Each write buffer is configured with local quality characteristics tailored to its specific processor channel, including dedicated resources and localized control logic. This allows each channel to maintain independent write ordering while participating in parallel operations, ensuring that local instruction order is preserved even as global throughput increases
3Reliability
If scoped persistence barriers are implemented to maintain write order, then reliability is improved, but device complexity increases
Solution Approach 1:
The write buffer system provides self-service functionality by automatically tracking write operations and maintaining persistence order without requiring complex external control mechanisms. Each buffer independently manages its own write queue and persistence timing, reducing the need for sophisticated barrier synchronization hardware while ensuring reliable ordered write-backs to non-volatile memory
Data Source
AI summary
A processing apparatus is provided that includes NVRAM and one or more processors configured to process a first set and a second set of instructions according to a hierarchical processing scope and process a scoped persistence barrier residing in the program after the first instruction set and before the second instruction set. The barrier includes an instruction to cause first data to persist in the NVRAM before second data persists in the NVRAM. The first data results from execution of each of the first set of instructions processed according to the one hierarchical processing scope. The second data results from execution of each of the second set of instructions processed according to the one hierarchical processing scope. The processing apparatus also includes a controller configured to cause the first data to persist in the NVRAM before the second data persists in the NVRAM based on the scoped persistence barrier.