Scoreboard Pixel Processing for Mobile Graphics
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Solution Overview
Problem
Conventional multimedia processors for image and video processing are computationally intensive and power-hungry, making them unsuitable for mobile applications, which require efficient and high-performance processing for tasks like video encoding and 3D gaming.
Innovation Solution
A multimedia processing system utilizing scoreboarding techniques to manage parallel processing of pixel fragments, ensuring correct ordering and efficient memory access through a scheduler and scoreboard system, integrated into a multimedia processor with dedicated hardware pipelines for low power consumption and high performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional multimedia processors are used for image and video processing, then processing capability is improved, but power consumption increases
Solution Approach 1:
The patent segments the pixel processing into separate threads organized by scanline, allowing independent parallel processing. Each thread handles a specific scanline, enabling fine-grained parallelism that reduces overall processing time while maintaining power efficiency through selective activation of processing units.
Solution Approach 2:
The patent introduces a scanline-based dimensional organization for thread allocation, transitioning from traditional block-based processing to line-based processing. This dimensional change enables more efficient memory access patterns and better cache utilization, improving processing capability without proportionally increasing power consumption.
2Productivity
If parallel processing is used to improve processing speed, then productivity is improved, but memory access ordering becomes complex
Solution Approach 1:
The patent segments memory access into scanline-based threads, where each thread has a well-defined memory access sequence. This segmentation simplifies ordering requirements because threads process independent scanlines, eliminating complex inter-thread memory ordering constraints while maintaining parallel processing speed benefits.
Solution Approach 2:
The patent implements feedback mechanisms through thread synchronization primitives that coordinate memory access between parallel threads. This feedback system ensures correct memory ordering without requiring complex global synchronization, allowing high productivity while managing the complexity of parallel memory access through localized synchronization.
Data Source
AI summary
In a graphics processing device, a plurality of processors write fragment shading results for order-dependent data to a buffer, according to the order in which the data is received. Fragment shading results for order-neutral data is written to the buffer one batch at a time. The order-dependent data comprises spatially overlapping data. Order-neutral data may not overlap. A scheduler controls the order of reception of one batch of data at a time by the processors. The order for receiving the order-dependent data may be determined. The plurality of processors may process the data in parallel. A writing order for writing results to a buffer from the processing in parallel, may be enforced. A portion of the processors may be instructed to wait before writing results to the buffer in a specified order. Processors signal when writing results to the buffer is complete.