SCR ESD Protection via One-Sided LDD MOSFET Gate Length
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Solution Overview
Problem
Silicon Controlled Rectifiers (SCRs) with high triggering voltage values are ineffective in protecting integrated circuits (ICs) from electrostatic discharge (ESD) damage, as they do not shunt ESD currents below typical operational voltages, leading to potential damage during normal operation.
Innovation Solution
Incorporating a one-sided Lightly Doped Drain (LDD) or non-LDD MOSFET structure in the SCR, which reduces the triggering voltage by adjusting the gate length, allowing for lower voltage triggering without excessive leakage current or parasitic capacitance, enabling effective ESD protection within the IC's operational voltage range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the SCR is designed with high triggering voltage values, then the device can maintain stability during normal operation, but it becomes ineffective in protecting ICs from ESD damage as it does not shunt ESD currents below typical operational voltages
Solution Approach 1:
The patent applies parameter changes by modifying the MOSFET gate length parameter to reduce the triggering voltage of the SCR from high values (ineffective for ESD protection) to lower values within the IC's operational voltage range. This enables the SCR to shunt ESD currents effectively while maintaining stability during normal operation.
2Reliability
If the gate length is reduced to lower the triggering voltage, then ESD protection becomes effective within operational voltage range, but leakage current may increase excessively
Solution Approach 1:
The patent applies local quality by implementing a one-sided Lightly Doped Drain (LDD) structure in the MOSFET, where only the drain region has light doping while the source region remains heavily doped. This localized doping difference reduces the triggering voltage through the LDD region while maintaining low leakage current by preserving the heavy doping in the source region, thus resolving the contradiction between triggering voltage reduction and leakage current control.
3Reliability
If the SCR structure is modified to reduce triggering voltage, then ESD protection effectiveness improves, but parasitic capacitance and design complexity may increase
Solution Approach 1:
The patent applies segmentation by dividing the MOSFET drain region into two distinct segments: a lightly doped drain (LDD) region and a heavily doped drain region. This segmentation allows the LDD region to reduce triggering voltage while the heavily doped region maintains low leakage and minimal parasitic capacitance, achieving ESD protection without excessive complexity.
Solution Approach 2:
The patent applies universality by designing the one-sided LDD MOSFET structure to simultaneously achieve multiple functions: reducing triggering voltage for ESD protection, maintaining low leakage current, and keeping parasitic capacitance minimal. This multi-functional design avoids the need for separate structures for each function, thereby reducing overall design complexity.
Data Source
AI summary
Some demonstrative embodiments include devices and/or systems of a Silicon Controlled Rectifier (SCR). For example, a silicon controlled rectifier (SCR) may include a metal-oxide-semiconductor field-effect transistor (MOSFET), the MOSFET may include a gate; an N-type source region; a non-Lightly Doped Drain (LDD) N-type drain region; and a P-Well region extending between the N-type source region and the non-LDD N-type drain region, and extending between the non-LDD N-type drain region and a drain region of the gate.