SCR ESD Protection Layout for Low Trigger Voltage and Leakage
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Solution Overview
Problem
Existing electrostatic discharge protection devices for integrated circuits face challenges in meeting the requirements of low trigger voltage and low leakage current, especially with the development of semiconductor processes that reduce element sizes and operating voltages, leading to potential damage from electrostatic discharges.
Innovation Solution
A device incorporating a silicon-controlled rectifier (SCR) and a field effect transistor (FET) configuration, where the FET is connected to the SCR through strategically placed n+ and p+ regions, allowing for a low trigger voltage and reduced leakage current, thereby protecting internal circuits from electrostatic discharges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional electrostatic discharge protection devices are used, then they can protect integrated circuits from ESD, but they exhibit high trigger voltage and high leakage current which can damage low-voltage internal circuits
Solution Approach 1:
The emitter of the PNP BJT is divided into multiple p+ regions spaced apart from each other, with n+ regions positioned between them. This segmentation creates multiple discharge paths that distribute the ESD current, reducing the trigger voltage and leakage current while maintaining protection capability.
Solution Approach 2:
The patent introduces n+ regions specifically between the p+ regions to create localized low-resistance paths. These n+ regions are strategically positioned to control the discharge characteristics in specific areas, enabling low trigger voltage without increasing overall leakage current.
2Use of energy by moving object
If element sizes are reduced to lower power consumption, then operating voltage decreases, but electrostatic discharge becomes more harmful relative to the reduced operating voltage
Solution Approach 1:
The patent modifies the structural parameters of the SCR by introducing multiple p+ and n+ regions, which changes the electrical characteristics (trigger voltage and leakage current) to be compatible with reduced operating voltages while maintaining ESD protection against increasingly harmful relative ESD events.
3Device complexity
If a single p+ region is used in the emitter, then the structure is simple, but the trigger voltage is high and leakage current is excessive
Solution Approach 1:
The emitter is segmented into multiple p+ regions with n+ regions between them, transforming a simple single-region structure into a multi-region structure that achieves superior electrical characteristics while maintaining reasonable manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively lowers the trigger voltage and reduces leakage current, ensuring safe protection of internal circuits with low operating voltages while preventing signal distortion and device damage.
Implementation Method 1
a field effect transistor (FET) configured to, based on an electrostatic discharge occurring between an anode of the first silicon-controlled rectifier and a cathode of the first silicon-controlled rectifier, trigger the first silicon-controlled rectifier
Data Source
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AI summary
A device includes: a first silicon-controlled rectifier comprising a first PNP bipolar junction transistor (BJT) and a first NPN BJT in which bases and collectors are crosscoupled; and a field effect transistor (FET) configured to, based on an electrostatic discharge occurring between an anode of the first silicon-controlled rectifier and a cathode of the first silicon-controlled rectifier, trigger the first silicon-controlled rectifier. An emitter of the first PNP BJT corresponds to a plurality of first p+ regions being spaced apart from each other in a first direction. The FET is connected to the first silicon-controlled rectifier through at least one first n+ region disposed between the plurality of first p+ regions.