SCR Gate Layout for Fine Trigger Voltage Tuning
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Solution Overview
Problem
Current techniques for adjusting the trigger voltage (Vtrig) of semiconductor controlled rectifiers, such as incorporating a field effect transistor (FET) or gate-induced drain leakage (GIDL), do not allow for fine-tuning of Vtrig to optimize performance.
Innovation Solution
A semiconductor structure with on-well gates that can remain floating or be biased to enable fine-tuning of Vtrig using gate leakage current, featuring a semiconductor layer with Nwell and Pwell regions and offset gates separated from junctions and diffusion regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional techniques (FET, GIDL, or field association) are used to adjust trigger voltage, then the trigger voltage can be adjusted, but fine-tuning capability is insufficient
Solution Approach 1:
The gate structure is divided into multiple independent gates (first gate adjacent to Nwell, second gate adjacent to Pwell, and optionally third gate adjacent to third well). Each gate can be independently biased to control trigger voltage, enabling fine-grained adjustment and precise control that conventional single-gate techniques cannot achieve.
Solution Approach 2:
The invention changes the electrical parameters (bias voltages) applied to each gate to control the trigger voltage. By varying the bias conditions on different gates, the trigger voltage can be precisely tuned. Additionally, the physical parameters (gate positions, diffusion region configurations) are optimized to enable fine-tuning capability.
2Adaptability or versatility
If gate structure is incorporated into SCR to adjust trigger voltage, then trigger voltage adjustment is enabled, but device complexity increases
Solution Approach 1:
The gate structures are integrated directly into the SCR device architecture, with gates positioned adjacent to the wells within the semiconductor layer. This merging approach enables trigger voltage adjustment functionality while maintaining a compact structure that does not significantly increase overall device complexity.
Solution Approach 2:
The multiple gates serve multiple functions: they control trigger voltage, enable fine-tuning, and can be biased in various configurations to achieve different operational characteristics. This multi-functionality justifies the added structural elements by providing enhanced control capabilities.
3Ease of operation
If gate is positioned close to junction for control, then control effectiveness is improved, but overlap with diffusion regions or junctions causes unwanted effects
Solution Approach 1:
Each gate is positioned in a specific location adjacent to a particular well (first gate to Nwell, second gate to Pwell, third gate to third well), creating localized control zones. This local positioning enables effective control of trigger voltage while avoiding overlap with diffusion regions and junctions, preventing unwanted effects.
Solution Approach 2:
The gates act as intermediaries between the control signals and the trigger mechanism. By positioning gates adjacent to wells rather than directly at junctions, they mediate the control function while maintaining appropriate spatial separation to avoid harmful overlaps with diffusion regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables precise adjustment of Vtrig through gate leakage current, improving the performance of semiconductor controlled rectifiers by allowing for smaller and more precise adjustments.
Implementation Method 1
utilizing gate leakage current to finely tune the trigger voltage
Implementation Method 2
incorporating a gate structure into the SCR and using a field associated with the gate structure to adjust Vtrig
Data Source
AI summary
Disclosed structures include a semiconductor controlled rectifier or bi-directional semiconductor controlled rectifier with a trigger voltage (Vtrig) that is tunable. Some structures include a semiconductor controlled rectifier with an Nwell and Pwell in a semiconductor layer, with a P-type diffusion region in the Nwell, and with an N-type diffusion region in the Pwell. Gate(s) on the well(s) are separated from the junction between the wells and from the diffusion regions. Other structures include a bidirectional semiconductor controlled rectifier with a Pwell between first and second Nwells in a semiconductor layer, with first P-type and N-type diffusion regions in the first Nwell, and with second P-type and N-type diffusion regions in the second Nwell. Gate(s) on the well(s) are separated from junctions between the Nwells and the Pwell and from any diffusion regions. In these structures, the gate(s) can be left floating or biased to tune Vtrig using gate leakage current.