SCR Structure with Guard Ring for ESD Protection
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Solution Overview
Problem
Integrated circuits, particularly those with CMOS devices, are susceptible to electrostatic discharge (ESD) events due to shrinking device dimensions, leading to potential damage from large and damaging ESD currents, necessitating improved ESD protection mechanisms.
Innovation Solution
A silicon controlled rectifier (SCR) device structure with a four-layer structure of doped regions forming p-n junctions, where layers with different electrical resistivities are strategically positioned to enhance ESD protection by maintaining a high-impedance state until an ESD event, then switching to a low-impedance conductive state to direct ESD current to ground.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dimensions are shrunk to increase integration density, then productivity and integration density improve, but susceptibility to ESD events and ESD current damage increases
Solution Approach 1:
The patent introduces a p-type guard ring as an intermediary structure between the n-well and substrate. This guard ring acts as a mediator that intercepts and controls the ESD current path, preventing direct high-current flow through sensitive CMOS devices. The guard ring structure with specific doping concentration and geometry serves as a protective intermediary that manages ESD energy dissipation.
Solution Approach 2:
The patent applies local quality by creating regions with different doping concentrations and material properties at specific locations. The p-type guard ring has higher doping concentration than surrounding areas, creating localized regions of high carrier concentration that control current flow. Different sections of the device structure have optimized local properties to handle ESD stress while maintaining normal operation elsewhere.
2Reliability
If an SCR ESD protection device is implemented, then ESD current protection improves, but parasitic leakage increases and junction breakdown voltage decreases
Solution Approach 1:
The patent optimizes multiple parameters of the SCR structure including doping concentrations, junction depths, and geometric dimensions to balance ESD protection with leakage control. By carefully adjusting the p-type guard ring doping concentration and the n-well depth, the patent achieves a compromise where the SCR triggers at appropriate voltages while minimizing parasitic leakage paths. The parameters are tuned to ensure the holding voltage remains above normal operating voltages.
Solution Approach 2:
The patent uses localized regions with different electrical properties to control current flow. High-resistivity regions are created in specific areas to block parasitic leakage, while low-resistivity regions are positioned to facilitate ESD current flow when needed. The p-type guard ring creates localized high-field regions that control breakdown characteristics without affecting entire device regions.
3Reliability
If layers with different electrical resistivities are positioned at p-n junctions, then junction breakdown voltage improves and parasitic leakage reduces, but device complexity increases
Solution Approach 1:
The patent segments the device structure into distinct functional layers with different doping concentrations and material properties. The structure is divided into the n-well region, p-type guard ring region, and substrate region, each with optimized properties. This segmentation allows independent optimization of each region's characteristics to achieve desired breakdown voltage and leakage control without requiring complete redesign of the entire device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The SCR device structure effectively reduces parasitic leakage and improves junction breakdown voltage, providing enhanced ESD protection by directing ESD currents away from sensitive internal circuits, thus preventing damage during ESD events.
Implementation Method 1
The second layer is comprised of a second material with a higher electrical resistivity than the first material
Implementation Method 2
Chips with complementary metal-oxide-semiconductor (CMOS) devices may be exposed to electrostatic discharge (ESD) events
Implementation Method 3
the ESD protection device is configured to change to a low-impedance, conductive state to direct the ESD current to ground
Data Source
AI summary
Device structures and design structures for a silicon controlled rectifier, as well as methods for fabricating a silicon controlled rectifier. The device structure includes first and second layers of different materials disposed on a top surface of a device region containing first and second p-n junctions of the silicon controlled rectifier. The first layer is laterally positioned on the top surface in vertical alignment with the first p-n junction. The second layer is laterally positioned on the top surface of the device region in vertical alignment with the second p-n junction. The material comprising the second layer has a higher electrical resistivity than the material comprising the first layer.