Silicon Controlled Rectifier Layout Area Reduction
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Solution Overview
Problem
Existing silicon controlled rectifiers (SCRs) for electrostatic discharge (ESD) protection devices often require large cell areas and increased manufacturing costs due to multiple wells or deep N-well manufacturing processes, which can lead to increased layout area and costs.
Innovation Solution
A silicon-controlled rectifier design that includes a substrate, a well, and multiple doped regions with specific conductivity types, where the deep doped regions are used to reduce the layout area and manufacturing costs by allowing electrical isolation without shallow trenches, thereby reducing leakage current and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple wells or deep N-well manufacturing process is used, then ESD protection function is improved, but layout area and manufacturing cost are increased
Solution Approach 1:
The patent merges multiple well structures into a single deep P-well structure. The SCR device is formed within this unified deep well, eliminating the need for separate N-well and P-well regions. This consolidation reduces the overall layout area while maintaining the ESD protection functionality through the deep well's ability to provide sufficient isolation and breakdown voltage.
Solution Approach 2:
The patent transitions from a planar multi-well structure to a vertically extended deep well structure. By increasing the depth dimension of the single P-well (achieving deeper junction depths), the design achieves better electrical isolation and ESD performance without expanding the lateral footprint, thus reducing layout area.
2Reliability
If multiple wells or deep N-well manufacturing process is used, then ESD protection function is improved, but manufacturing cost is increased
Solution Approach 1:
The patent combines multiple manufacturing steps and structures into a simplified single deep P-well process. By eliminating the need for separate N-well formation steps and multiple well implantation processes, the manufacturing complexity is reduced, leading to lower production costs while maintaining ESD protection effectiveness.
Solution Approach 2:
The patent extracts and eliminates the complex deep N-well manufacturing process from the fabrication sequence. By removing this costly and complex process step while retaining ESD protection through the simplified deep P-well structure, manufacturing costs are reduced without sacrificing reliability.
3Reliability
If conventional SCR structure is used, then ESD protection is provided, but leakage current is increased
Solution Approach 1:
The patent addresses leakage current by extending the isolation depth vertically rather than expanding laterally. The deep P-well structure achieves deeper junction depths that provide better electrical isolation between the SCR device and surrounding circuits, effectively reducing leakage current while maintaining ESD protection in the vertical dimension.
Data Source
AI summary
A silicon controlled rectifier includes a substrate, a well, a deep doped region, a first doped region, a second doped region, a third doped region, and a fourth doped region. The well is disposed on the substrate and underneath a cell region. The deep doped region is disposed in the well. The first doped region has a first conductivity type, and is disposed in the well. The second doped region and third doped region have the first conductivity type and are disposed on the deep doped region. The fourth doped region has a second conductivity type, and is disposed between the second doped region and the third doped region. The fourth doped region is disposed on the deep doped region, and is electrically isolated from the well through the deep doped region, the second doped region, and the third doped region.