Multi-bit Scramble Hardware via Bit Width Expansion
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Solution Overview
Problem
The existing single-bit scramble and descramble implementations in USB3.1 and PCI-Express 3.0 protocols result in significant hardware delay due to the need for multiple iterations, limiting the operating frequency and overall system performance.
Innovation Solution
A data bit width expansion method for scramble and descramble hardware implementation, which eliminates redundant terms and reduces hardware delay by performing XOR operations across multiple bits simultaneously, utilizing a linear feedback shift register based on the polynomial X23+X21+X16+X8+X5+X2+1.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If single-bit scramble and descramble implementations are used as defined in USB3.1 and PCI-Express 3.0 protocols, then the data transmission follows protocol standards, but significant hardware delay occurs due to multiple iterations
Solution Approach 1:
The patent transitions from single-bit processing to multi-bit parallel processing by expanding the data bit width. Instead of processing one bit at a time through multiple iterations, the invention processes multiple bits simultaneously using expanded linear feedback shift registers and parallel XOR operations, thereby reducing hardware delay while maintaining protocol compliance
Solution Approach 2:
The patent divides the data bus into multiple parallel channels, each handling a portion of the data bits. By segmenting the processing into parallel paths with dedicated linear feedback shift registers and XOR gates for each bit position, the system eliminates sequential iteration delay while maintaining the required scramble/descramble functionality
2Reliability
If multiple iterations are performed for each bit in single-bit implementation, then thorough scramble/descramble processing is achieved, but operating frequency is limited
Solution Approach 1:
The patent enables continuous parallel processing across all data bits simultaneously. By implementing multi-bit linear feedback shift registers that operate in parallel with corresponding XOR gates for each bit position, the system performs complete scramble/descramble processing in a single cycle rather than through multiple sequential iterations, thereby enabling higher operating frequencies
Solution Approach 2:
The patent combines multiple single-bit processing operations into a unified multi-bit parallel processing structure. By merging the linear feedback shift registers and XOR operations for all data bits into a single synchronized operation, the system achieves thorough processing of all bits simultaneously, eliminating the need for multiple iterations and increasing operating frequency
Data Source
AI summary
A scramble and descramble hardware implementation method based on data bit width expansion. After expansion, redundant terms are eliminated, and scramble/descramble operation results within the current operation cycle and the value of the shift register after shifting are calculated at once. The present method exhibits advantageous effects with respect to the scramble and descramble polynomial defined by USB3.1 and PCI-Express3.0 protocols, and can obtain a relatively small hardware delay, so that the system can work at a higher frequency.