Scramble Circuits for Semiconductor Memory Address Distribution
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor memory devices using phase changeable materials often experience increased error ratios in memory cells adjacent to control blocks, leading to low yields due to differences in signal transmission characteristics, which are not effectively addressed by existing error-bit tests.
Innovation Solution
A semiconductor system with a module controller and scramble circuits for each semiconductor chip, which convert logical addresses into unique physical addresses based on address bit test commands, ensuring each chip selects different memory cells, thereby distributing error generation and reducing concentration in adjacent cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error-bit test is performed on semiconductor chips to detect manufacturing defects, then reliability of memory access is improved, but error ratio in adjacent cells increases due to signal transmission characteristics
Solution Approach 1:
The patent applies parameter changes by modifying the address mapping parameters through scramble circuits. Each semiconductor chip has a unique scramble circuit that transforms logical addresses into physical addresses using chip-specific scramble patterns, thereby changing the address parameters to distribute access patterns and reduce error concentration in adjacent cells.
Solution Approach 2:
The patent implements local quality by applying chip-specific scramble patterns that are unique to each semiconductor chip. This local differentiation in address scrambling ensures that each chip accesses different physical memory locations for the same logical address, thereby locally optimizing error distribution for each chip while maintaining overall system reliability.
2Device complexity
If logical addresses are directly mapped to physical addresses, then address translation simplicity is improved, but error concentration in adjacent memory cells increases
Solution Approach 1:
The patent changes address parameters by introducing scramble circuits that transform logical addresses into physical addresses using unique scramble patterns for each chip. This parameter transformation adds minimal complexity while effectively distributing error patterns across different physical locations, preventing error concentration in adjacent cells.
Solution Approach 2:
The scramble circuit acts as an intermediary between the logical address space and physical address space. It mediates the address translation process by introducing chip-specific scramble patterns, thereby decoupling the simplicity of logical addressing from the requirements of error distribution in physical memory locations.
3Stability of the object's composition
If same logical address maps to same physical address across chips, then address consistency is improved, but yield decreases due to adjacent cell errors
Solution Approach 1:
The patent applies local quality by making address mapping chip-specific through unique scramble patterns. While each chip has its own local address mapping rules, the system maintains overall consistency through standardized scramble circuit architecture and coordinated address management, thereby preserving stability while improving yield.
Solution Approach 2:
The patent changes the address mapping parameters to be chip-specific rather than uniform across all chips. By transforming logical addresses using unique scramble patterns for each chip, the system maintains address consistency within the standardized framework while distributing errors to improve overall productivity and yield.
Data Source
AI summary
A semiconductor system in accordance with an embodiment includes a module controller and a plurality of semiconductor chips configured to receive logical addresses from the module controller. The semiconductor system also includes a plurality of scramble circuits, with a scramble circuit provided for each of the plurality of semiconductor chips, configured to receive the logical addresses and to output corresponding physical addresses for the plurality of semiconductor chips. Each scramble circuit of the plurality of scramble circuits is configured to receive the same logical address and to output a corresponding physical address different from the physical addresses output by the other scramble circuits of the plurality of scramble circuits.