Self-Synchronous Scrambler for High-Speed Bus Data
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Solution Overview
Problem
Existing data communication protocols for high-speed networks, such as 100 Gbps and 1 Tbps, require wider internal datapaths or buses, leading to inefficiencies in scrambling and descrambling processes, particularly due to the need for multiple partial scramblers and complex state management in current self-synchronous scramblers.
Innovation Solution
A self-synchronous scrambler/descrambler design that uses an M-bit Scrambler State memory, a SOP/EOP Zero Inserter, Mid-Packet Word Logic, and a Barrel Shifter to efficiently scramble and descramble data by rotating the scrambler state and inserting zeros, eliminating the need for multiple partial scramblers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple partial scramblers are used to handle variable frame lengths, then scrambling coverage is improved, but device complexity increases
Solution Approach 1:
A single scrambler unit is designed to handle all possible frame lengths and positions by using a universal scrambling polynomial G(x) = x^43 + 1. The scrambler can process any data length from 1 to W bytes and any position within a bus word, eliminating the need for multiple specialized partial scramblers while maintaining full scrambling coverage.
Solution Approach 2:
The scrambler uses dynamic control signals (SOP_EOP, LAST_BYTE_POS) to adapt its operation to different frame lengths and positions. The scrambler state is dynamically updated based on the actual frame content, allowing a single static hardware unit to perform the work of multiple dynamic partial scramblers.
2Productivity
If wider internal datapaths are used to increase processing capacity, then productivity is improved, but the need for multiple partial scramblers increases device complexity
Solution Approach 1:
The scrambler is designed as a universal unit that can process data at the full width of the internal datapath (W bytes) in a single operation. This universal design works efficiently at any data width from 1 to W bytes, allowing the system to utilize wide datapaths for high-speed processing without requiring multiple parallel scrambler instances.
Solution Approach 2:
The scrambling operation is segmented into byte-level operations that can be efficiently parallelized across wide datapaths. By processing data in W-byte chunks and using the byte position of the last frame byte as a control parameter, the system can fully utilize wide internal buses while maintaining correct scrambling behavior.
3Device complexity
If a single scrambler handles all frame lengths, then device complexity is reduced, but adaptability to variable frame positions must be maintained
Solution Approach 1:
The scrambler uses feedback from frame delineation information (SOP_EOP signal and LAST_BYTE_POS) to adjust its operation. The position of the last byte of the frame within the bus word is fed back to the scrambler, which uses this information to correctly handle the variable frame position and update its internal state accordingly.
Solution Approach 2:
The frame delineation function identifies the position of the last byte of the frame before the scrambler processes the data. This preliminary identification of frame boundaries and positions allows the single scrambler to be properly configured for the upcoming scrambling operation, ensuring correct handling of variable frame positions.
Data Source
AI summary
A self-synchronous scrambler/descrambler and method for operating same are disclosed. A self-synchronous scrambler/descrambler comprises an M-bit Scrambler State memory for retaining M previously scrambled/descrambled bits, a SOP/EOP Zero Inserter for receiving replacing certain bytes of the bus word with a value of zero, a Mid-Packet Word Logic for scrambling/descrambling the received bits using the previously scrambled/descrambled bits from the M-bit Scrambler State memory; and a Barrel Shifter for rotating the M-bit Scrambler State memory backwards. The method for scrambling/descrambling bits, comprising receiving a bus word, replacing certain bytes of the bus word, scrambling/descrambling bits of the bus word by exclusive-ORing with previously scrambled/descrambled bits, retaining the scrambled/descrambled bits of the bus word; and rotating the scrambled/descrambled bits of the bus word backwards an amount.