Self-Synchronous Scrambler Error Correction for Multiplied Errors
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Solution Overview
Problem
Self-synchronous scramblers in telecommunications systems multiply transmission channel errors, leading to inefficiencies in error correction codes, as conventional techniques require more powerful Forward Error Correction (FEC) codes to handle replicated errors, which is inefficient and complex.
Innovation Solution
A method to correct errors by exploiting knowledge of the scrambler polynomial, allowing the use of a less powerful error correction code by processing data blocks in pairs and canceling replications of errors, thereby reducing the need for more powerful FEC codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If self-synchronous scramblers are used to prevent data interference between subscribers, then transmission reliability is improved, but error multiplication occurs which worsens error correction efficiency
Solution Approach 1:
The patent segments the data stream into blocks and processes error correction on a block-by-block basis. By dividing the continuous data stream into discrete blocks, the system can apply error correction codes to individual blocks independently, managing the multiplied errors in a controlled manner rather than attempting to correct all errors simultaneously across the entire stream.
Solution Approach 2:
The patent applies error correction codes preliminarily to data blocks before they are scrambled by the self-synchronous scrambler. By performing error correction preparation in advance, the system accounts for the upcoming error multiplication effect, selecting code parameters and redundancy levels that will be sufficient after scrambling but not excessive before it.
2Reliability
If more powerful FEC codes are used to handle replicated errors, then error correction capability is improved, but device complexity and bandwidth usage increase
Solution Approach 1:
The patent changes the parameters of the error correction code based on the scrambler's error multiplication characteristics. Instead of using fixed high-power FEC codes, the system selects code parameters (such as code rate, block length, and redundancy level) that are optimized for the specific error pattern produced by the self-synchronous scrambler, achieving sufficient correction capability with lower complexity.
Solution Approach 2:
The patent exploits the repetitive structure of multiplied errors by using the known scrambler polynomial to predict and cancel error replications. Rather than designing FEC codes to handle arbitrary error patterns, the system copies the known error pattern structure and uses it to simplify the correction process, reducing the required code strength.
3Ease of operation
If conventional error correction codes are used without exploiting scrambler knowledge, then implementation simplicity is maintained, but correction effectiveness decreases due to error multiplication
Solution Approach 1:
The patent introduces feedback by using the known scrambler polynomial as additional information in the error correction process. The receiver uses knowledge of the scrambler's structure to feed back constraints on the error pattern, allowing the error correction decoder to use this side information to improve its correction effectiveness without requiring more complex hardware.
Data Source
AI summary
Systems and methods correct multiplied errors generated by feedback taps in self-synchronous descramblers. The multiplication of errors degrades the performance of most linear cyclic error check codes. Disclosed techniques are general applicable to multiplied errors even when those errors are not confined to a single block. Disclosed techniques permit a reduction in the amount of forward error correction used. For example, in general, to correct t errors, a linear cyclic error correction code requires a Hamming distance of at least 1+(2t)[wt(s(x))]. Embodiments of the invention allow correcting the multiplied errors with a Hamming distance of only 1+(t)(1+wt(s(x))) over the block size n, wherein wt(s(x)) is the weight of the scrambler polynomial s(x).