Scrambler Logic Segmentation for High Speed Network Data
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Solution Overview
Problem
Scrambling data at line rates in high-speed communications networks, such as 100 G and 400 G Ethernet, is challenging due to the need to scramble an entire bus width of data during each clock cycle, which requires complex logic implementations that exceed the physical real estate available on a chip.
Innovation Solution
The method involves precomputing and storing the scramble key and data portions, allowing for efficient logical combination using a single 2-input exclusive OR gate to produce scrambled output data, thereby reducing the complexity of logic elements required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If an entire bus width of data is scrambled during each clock cycle, then line rate transmission is achieved, but the logic implementation complexity increases excessively
Solution Approach 1:
The patent segments the scrambling operation into two independent parts: a scramble key portion and a data portion. The scramble key portion is precomputed and stored in a lookup table, while the data portion is computed from the input data. This segmentation allows the complex scrambling function to be broken down into manageable components that can be efficiently implemented with simpler logic.
Solution Approach 2:
The patent applies preliminary action by precomputing the scramble key portion before the actual scrambling operation. The scramble key portion is computed in advance and stored in a lookup table, so that during line rate transmission, only the data portion needs to be computed and then combined with the precomputed key portion using simple XOR logic. This eliminates the need for complex real-time scrambling logic.
2Adaptability or versatility
If complex logic is used to scramble entire bus width data, then scrambling functionality is achieved, but chip real estate is exceeded
Solution Approach 1:
The patent divides the scrambling functionality into two segments: a precomputed scramble key portion stored in a lookup table and a data portion computed from input data. This segmentation reduces the logic required on-chip to only the essential XOR combination operation, significantly reducing the area needed while maintaining full scrambling functionality.
Solution Approach 2:
The patent uses a lookup table to store precomputed scramble key portions, effectively copying the complex scrambling logic into a pre-computed form. This allows the actual hardware implementation to use simple XOR operations instead of complex logic, reducing chip area while preserving the scrambling function's adaptability and versatility.
Data Source
AI summary
The subject matter described herein includes methods, systems, and computer readable media for efficiently scrambling data in high speed communications networks. One exemplary method includes, in a network equipment test device, providing a scrambler for scrambling data to be transmitted to a device under test. Scrambling the data includes separating a scrambling algorithm into a scramble key portion and a data portion. Scrambling the data further includes pre computing and storing the scramble key portion. Scrambling the data further includes precomputing and storing the data portion. Scrambling the data further includes logically combining the precomputed scramble key portion with the precomputed data portion to produce a data bus width scrambled output data. The method further includes transmitting the scrambled output data over a network to the device under test.