Scrambling Circuits Mitigate Row Hammering in Memory Systems
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Solution Overview
Problem
As memory integration increases, the coupling effect between word lines leads to data damage in memory cells due to row hammering, where frequently activated word lines disturb adjacent cells, causing data deterioration and potential system malfunctions.
Innovation Solution
A memory system with scrambling circuits in multiple memories that share common addresses, where each scrambling circuit generates a unique scrambled address by selectively inverting bits of the common address, ensuring that neighboring word lines are activated at most in one memory, thereby minimizing the impact of row hammering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory integration degree increases, then storage capacity is improved, but coupling effect between word lines increases causing row hammering
Solution Approach 1:
The patent divides the memory system into multiple independent memory devices, each with its own word lines. By segmenting the address space across multiple memories, the system reduces the coupling effect between word lines in any single memory, thereby mitigating row hammering while maintaining high storage capacity through parallel access to multiple memories.
Solution Approach 2:
The patent introduces an additional dimension by using multiple memory devices with different scrambling patterns. Instead of only varying addresses within a single memory, the system combines memory selection with address scrambling to achieve the same effect of distributing access patterns, thereby reducing row hammering impact.
2Quantity of substance
If word line spacing decreases, then memory density is improved, but coupling effect between neighboring word lines increases
Solution Approach 1:
The patent applies different scrambling patterns to different memory devices, creating local variations in word line activation patterns. This local quality differentiation ensures that even though word line spacing is reduced for higher density, the coupling effect is mitigated because adjacent word lines in different memories follow different activation sequences.
3Speed
If frequently activated word lines are accessed, then data access speed is improved, but data in adjacent memory cells is damaged
Solution Approach 1:
The patent introduces scrambling circuits as intermediary components between the address generation unit and the memory devices. These scrambling circuits transform the address signals before they reach the memories, effectively mediating the interaction between frequently accessed word lines and adjacent cells to prevent row hammering while maintaining fast access speeds.
Solution Approach 2:
The patent creates multiple copies of the same data across different memory devices with different scrambling patterns. When data is accessed, multiple copies are read simultaneously from different memories, and the results are combined. This copying approach maintains data integrity by providing redundancy while enabling fast access through parallel operations.
Data Source
AI summary
A memory system includes a first memory and a second memory that share common addresses received from a memory controller, wherein the first memory includes a first scrambling circuit suitable for scrambling a common address to generate a first scrambled address designating a word line to be activated in the first memory, and the second memory includes a second scrambling circuit suitable for scrambling the common address to generate a second scrambled address designating a word line to be activated in the second memory, and the first scrambling circuit and the second scrambling circuit perform a scrambling operation in such a manner that neighboring word lines, adjacent to a word line selected by a first common address, are selected a most in one memory among the first memory and the second memory by a second common address other than the first common address.