Low-Latency Scratch Memory Path for Vector Stack Access
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Solution Overview
Problem
High latency in vector memory access operations, particularly for vector stack access instructions, due to the use of complex pipeline stages in existing memory hierarchies, leads to inefficient processing in highly parallel data applications.
Innovation Solution
Implementing a dual execution pipeline system in the local memory subsystem, where one pipeline bypasses complex stages like tag coalescing and bank coalescing, specifically designed for vector stack access instructions, to reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single complex execution pipeline is used for all vector memory accesses, then the pipeline can handle various complex address offsetting and coalescing operations, but the latency for simple vector stack access instructions becomes unnecessarily high
Solution Approach 1:
The execution pipeline is segmented into two separate pipelines: a first execution pipeline for vector stack access instructions and a second execution pipeline for other vector memory access instructions. This segmentation allows each pipeline to be optimized for its specific workload, with the first pipeline having reduced complexity and lower latency for stack accesses, while the second pipeline handles complex address offsetting and coalescing operations.
2Adaptability or versatility
If multiple complex pipeline stages are included to support per-lane address offsets and tag address coalescing, then gather and scatter operations can be performed, but the overall memory access latency increases
Solution Approach 1:
The pipeline is divided into specialized paths: the first execution pipeline handles simple stack accesses without complex stages, while the second execution pipeline includes the necessary complex stages (per-lane address offsetting, tag address coalescing, gather and scatter) only when needed for non-stack memory accesses, thereby maintaining speed for simple operations.
3Stability of the object's composition
If in-order processing is used for vector memory instructions, then instruction ordering is maintained, but unnecessary high latency is incurred for instructions that do not require complex pipeline stages
Solution Approach 1:
The in-order processing requirement is satisfied separately for each pipeline. The first execution pipeline maintains in-order processing for vector stack access instructions, while the second execution pipeline maintains in-order processing for other vector memory instructions. This allows each instruction type to benefit from optimized, lower-latency processing while preserving the necessary ordering guarantees.
Data Source
AI summary
An apparatus and method for efficiently processing vector memory accesses on an integrated circuit. In various implementations, a computing system includes a processing circuit with multiple compute circuits for executing wavefronts of a parallel data application. Each compute circuit includes a local memory subsystem for accessing data not found in vector register files of the compute circuit. The local memory subsystem includes a first execution pipeline and a second execution pipeline. The second execution pipeline processes vector stack access instructions that access temporary data such as stack data of a function call used by each wavefront that is generated based on the function call. The first execution pipeline processes other types of vector memory access instructions and includes multiple complex pipeline stages not found in the second execution pipeline. Thus, the second execution pipeline has a latency less than the latency of the first execution pipeline.