Scratchpad Memory Banks for Energy-Efficient System-in-Package
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Solution Overview
Problem
Traditional cache-based memory structures are energy inefficient and not suitable for embedded systems due to increased system size and energy costs, as they require excessive data transfer and hardware management, which limits their adaptability and predictability.
Innovation Solution
A memory hierarchy with software-controlled scratchpad memory that allows dynamic allocation of data across different memory levels, using a data access controller to manage scratchpad memory banks and forward requests to cache or main memory based on availability, enabling flexible data allocation and reducing energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If cache memory is used to increase access speed, then speed is improved, but energy consumption increases
Solution Approach 1:
The memory system is segmented into multiple scratchpad memory banks (L1, L2, L3) organized in a hierarchical structure, each bank handling specific data access patterns. This segmentation allows the system to serve different access speed requirements from different banks while managing energy consumption independently for each bank, avoiding the energy overhead of a unified cache system.
Solution Approach 2:
Instead of using traditional cache memory that automatically manages data with hardware control, the patent inverts the approach by using scratchpad memory banks that are explicitly managed by software (compiler or operating system). This inversion eliminates the need for complex hardware control circuits, tag comparison logic, and automatic data transfer mechanisms, thereby reducing energy consumption while maintaining flexible data access.
2Speed
If cache memory is used to increase access speed, then speed is improved, but device complexity increases
Solution Approach 1:
The patent extracts the complex hardware control mechanisms from the memory system by removing cache control circuits, tag arrays, and automatic data transfer logic. Instead, it uses simple scratchpad memory banks with direct software control, taking out the complexity while maintaining the essential function of fast data access through explicit software management.
Solution Approach 2:
The scratchpad memory banks are designed to be self-service memory structures that do not require external control circuits for data management. The compiler or operating system directly manages data placement and access, eliminating the need for complex hardware control logic that would otherwise be required to manage cache memory operations.
3Productivity
If cache memory is used to improve performance, then productivity is improved, but adaptability decreases
Solution Approach 1:
The patent implements dynamic adaptability by allowing the software (compiler or operating system) to dynamically manage data placement in scratchpad memory banks based on runtime conditions, access patterns, and application requirements. This dynamic management enables the system to adapt to different workloads and applications, providing versatility while maintaining high performance through optimized data access.
Data Source
AI summary
The present disclosure relates to a memory hierarchy for a system-in-package. An example memory hierarchy is connectable to a processor via a memory management unit arranged for translating a virtual address sent by the processor into a physical address. The memory hierarchy has a data cache memory and a memory structure having at least a L1 memory array comprising at least one cluster. The memory structure comprises a first data access controller arranged for managing one or more banks of scratchpad memory of at least one of the clusters of at least the L1 memory array, comprising a data port for receiving at least one physical address and arranged for checking at run-time, for each received physical address, bits of the physical address to see if the physical address is present in the one or more banks of the at least one cluster of at least the L1 memory array.