Scribe Lane Alignment Keys for 3D Memory Chip Integration
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Solution Overview
Problem
The integration of semiconductor devices is limited by the area occupied by unit memory cells, and existing three-dimensional semiconductor devices face challenges in improving operation reliability due to the placement of alignment keys within chip areas, which can hinder the degree of integration and manufacturing efficiency.
Innovation Solution
The semiconductor device incorporates alignment keys in the scribe lane area rather than the chip areas, with alternately stacked material layers and protrusion parts that serve as reference points for mask alignment, allowing for improved chip formation and integration without adding separate processes, and includes a method of manufacturing that forms these keys and stacks in the scribe lane area to enhance chip area structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If alignment keys are placed within chip areas to enable mask alignment, then alignment precision is improved, but the area available for memory cells is reduced, decreasing the degree of integration
Solution Approach 1:
The substrate is divided into chip areas and scribe lane areas, with alignment keys specifically placed in the scribe lane areas. This segmentation allows the alignment function to be separated from the chip area, enabling mask alignment while preserving the full chip area for memory cell formation.
Solution Approach 2:
The scribe lane area serves as an intermediary region that hosts alignment keys and other auxiliary structures. This intermediary zone mediates between the need for alignment features and the requirement to maximize chip area, allowing both objectives to be achieved simultaneously.
2Manufacturing precision
If alignment keys are formed in separate processes to ensure proper placement, then alignment precision is improved, but the number of manufacturing steps increases, reducing productivity
Solution Approach 1:
The formation of alignment keys is merged with the formation of stacks in the scribe lane area. Both structures are created simultaneously using the same material layers and processing steps, eliminating the need for separate alignment key formation processes and thereby maintaining high productivity.
Solution Approach 2:
The stacks formed in the scribe lane area serve multiple functions: they act as alignment keys with protrusion parts for mask alignment, and simultaneously serve as structural elements in the scribe lane region. This multi-functionality eliminates the need for dedicated alignment key structures and their associated manufacturing steps.
3Area of moving object
If three-dimensional stacked structures are implemented to improve integration density, then the degree of integration is improved, but operation reliability may be compromised due to increased complexity
Solution Approach 1:
Alignment keys with protrusion parts are formed in advance within the stacked structures of the scribe lane area. These pre-formed alignment features enable accurate mask alignment for subsequent processing steps, ensuring that the complex three-dimensional structures in chip areas can be fabricated with high precision and reliability.
Solution Approach 2:
The patent replaces traditional mechanical alignment methods with a system based on protrusion parts that provide physical reference points for mask alignment. This substitution enables more precise and reliable alignment in three-dimensional structures compared to conventional mechanical approaches.
Data Source
AI summary
A semiconductor device may include a substrate including chip areas and a scribe lane area that is disposed between the chip areas, a first stack disposed in the scribe lane area and including first material layers and second material layers that are alternately stacked, and alignment keys disposed within the first stack including first protrusion parts that protrude from an upper surface of the first stack, respectively.