Semiconductor Scribe Lane Layout to Protect Bonding Pads From Cracks

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Solution Overview

Problem

Existing semiconductor manufacturing processes face challenges in reducing defects caused by cracks during the wafer cutting process, particularly affecting bonding pads due to the propagation of cracks from metal patterns in scribe lanes.

Innovation Solution

A method involving laser irradiation along the center lines of scribe lanes to form modified portions in the semiconductor substrate, followed by polishing and separation into device regions, with metal patterns offset to minimize crack propagation to bonding pads.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If metal patterns are arranged in scribe lanes during wafer cutting, then interconnection and electrical connection are enabled, but crack propagation occurs from metal patterns to bonding pads causing defects

Engineering Contradiction:
Improvebonding pad integrityVSAvoidcrack propagation
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies asymmetry by offsetting the metal patterns from the center line of the scribe lane towards one side, creating an asymmetric arrangement. This asymmetric positioning ensures that cracks propagating from metal patterns during wafer cutting do not symmetrically affect bonding pads on both sides, thereby reducing the probability of bonding pad defects while maintaining electrical interconnection functionality

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent applies local quality by creating a crack-resistant structure in specific localized regions. The offset metal pattern arrangement creates zones with different crack propagation characteristics - the region closer to the metal pattern has enhanced crack resistance, while bonding pads are positioned in protected zones, providing localized quality enhancement where it is most needed

Inventive Principle:
Principle #3Local quality

2Reliability

If laser irradiation is applied along scribe lane center lines to form modified portions, then crack resistance is improved, but additional process steps and complexity are introduced

Engineering Contradiction:
Improvecrack resistanceVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by performing laser irradiation to create modified portions in the substrate along the scribe lane center lines before the wafer cutting process. These pre-formed modified portions act as crack-arresting features that prevent crack propagation during subsequent cutting operations, improving reliability by addressing potential crack issues before they occur

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent replaces mechanical crack prevention methods with a laser-based modification approach. Instead of relying solely on mechanical design features or material selection, the invention uses laser irradiation to create modified portions that provide crack resistance, substituting a thermal/optical process for traditional mechanical crack prevention strategies

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Reduces defects in bonding pads by mitigating crack propagation through offset metal pattern arrangements, enhancing the reliability and integrity of semiconductor devices.

Implementation Method 1

irradiating a laser along a center line of a scribe lane of a substrate structure forms modified portions in the semiconductor substrate

Methodology Applied
Scientific EffectLaser irradiation: Laser

Implementation Method 2

irradiating a laser along the center line of the scribe lane forms modified portions in the semiconductor substrate

Methodology Applied
Scientific EffectLaser heating: Heating

Implementation Method 3

polishing a lower surface of the semiconductor substrate to reduce a thickness of the substrate structure

Methodology Applied
Scientific EffectMechanical polishing: Abrasion

Data Source

PatentUS20260052928A1Method of manufacturing semiconductor device
Publication Date: 2026.02.19 SAMSUNG ELECTRONICS CO LTD
  • US20260052928A1 patent drawing
  • US20260052928A1 patent drawing
  • US20260052928A1 patent drawing

AI summary

A method of manufacturing a semiconductor device includes cutting a substrate structure along a scribe lane to separate a plurality of semiconductor devices from the substrate structure. The substrate structure includes a plurality of device regions and the scribe lane separates the plurality of device regions. Each of the plurality of device regions includes a first side and a second side opposite the first side. Each of the plurality of device regions includes bonding pads arranged along the first side, and bonding pads are absent on a region adjacent to the second side. The plurality of device regions are arranged such that the first side and the second side of adjacent device regions face each other and the scribe lane is therebetween in the substrate structure. The substrate structure further includes metal patterns arranged closer to the second side than to the first side in the scribe lane.