Scribe Lane Segmentation for Laser Sawing Crack Control
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Solution Overview
Problem
The use of low-k dielectric materials in semiconductor wafers leads to difficulties in vertical crack progression during the laser sawing process, resulting in peeling phenomena of the oxide layer in the scribe lane, as the low-k dielectric material is weaker than conventional insulating layers, hindering efficient separation of semiconductor chips.
Innovation Solution
A semiconductor chip design that includes a scribe lane structure with a lower interlayer insulating layer, a circuit structure, and a pad structure, where the circuit and pad structures are spaced apart in the longitudinal direction, and a stacked structure comprising a low-k dielectric layer and an upper interlayer insulating layer, with metal pad layers and passivation layers, facilitating vertical crack progression and preventing peeling by exposing the upper surface and sidewalls of the lower interlayer insulating layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If low-k dielectric material is used as insulating layer, then parasitic capacitance between interconnection layers is inhibited, but crack progression is blocked and peeling phenomenon occurs during laser sawing
Solution Approach 1:
The scribe lane is divided into multiple segments by introducing circuit structures and open regions that create discontinuities. These segmented regions act as crack stoppers to prevent horizontal crack propagation while allowing vertical crack progression, thus enabling reliable chip separation despite the presence of weak low-k dielectric material
Solution Approach 2:
Metal pad layers and circuit structures are introduced as intermediary elements within the scribe lane. These intermediaries provide mechanical support and act as barriers to horizontal crack propagation, mediating between the weak low-k dielectric material and the requirements for reliable chip separation
2Object-affected harmful factors
If low-k dielectric material is used, then dielectric strength is reduced for capacitance inhibition, but structural strength decreases leading to peeling during sawing
Solution Approach 1:
The scribe lane structure employs a composite configuration combining low-k dielectric material with metal pad layers and oxide layers. This composite structure leverages the low-k material's electrical properties while using the metal and oxide layers to provide mechanical strength and prevent peeling during the sawing process
Solution Approach 2:
Different regions of the insulating structure are assigned different materials and properties: the low-k dielectric material is used in interconnection regions for capacitance reduction, while metal pad layers and oxide layers are strategically placed in the scribe lane regions to provide localized mechanical strength and crack resistance
3Ease of manufacture
If continuous insulating layer is used in scribe lane, then manufacturing is simplified, but crack progression is blocked and separation efficiency decreases
Solution Approach 1:
The continuous insulating layer in the scribe lane is segmented into discrete regions separated by open regions and circuit structures. This segmentation creates controlled discontinuities that facilitate vertical crack progression while maintaining manufacturing feasibility through standard photolithography and etching processes
Solution Approach 2:
The scribe lane structure is pre-configured with circuit structures, open regions, and metal pad layers before the laser sawing process. These pre-formed features create predetermined pathways for crack propagation, ensuring efficient chip separation without requiring additional processing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables efficient separation of semiconductor chips without peeling of the upper interlayer insulating layer or passivation layers, ensuring stable and reliable chip separation by supporting crack progression through the metal pad layers.
Implementation Method 1
In a laser sawing process, cracks are formed in a back surface of a wafer
Data Source
AI summary
A semiconductor chip includes a substrate including: a main chip region; and a scribe lane surrounding the main chip region; a lower interlayer insulating layer disposed on the substrate in the scribe lane; a circuit structure disposed on the lower interlayer insulating layer in the scribe lane; and a pad structure disposed on the lower interlayer insulating layer. The circuit structure and the pad structure are disposed to be spaced apart from each other in a longitudinal direction of the scribe lane.