Scribe Lane Test Circuit Layout for Reliable 3D Semiconductor Cutting
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Solution Overview
Problem
The integration of semiconductor devices is limited by the area occupied by unit memory cells, and existing methods struggle to enhance operational reliability, particularly in three-dimensional semiconductor devices where memory cells are stacked on a substrate.
Innovation Solution
A semiconductor device and manufacturing method that include forming a test circuit and a dummy structure in the scribe lane area between chip areas, with interconnection structures connecting test pads and circuits, allowing for improved integration and protection of chip areas during substrate cutting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are stacked in three-dimensional structure to improve integration, then the degree of integration is improved, but operational reliability deteriorates due to increased stress and structural complexity
Solution Approach 1:
The substrate is divided into chip areas and scribe lane areas, with the scribe lane further segmented into line areas and cross areas. Test circuits are placed in cross areas while dummy structures are placed in line areas, allowing stress and testing functions to be separated from the chip areas, thus maintaining reliability while achieving high integration through 3D stacking
Solution Approach 2:
Dummy structures are formed in the scribe lane area before the substrate cutting process. These dummy structures serve as preliminary protective elements that absorb stress during the subsequent cutting operation, preventing stress from being transmitted to the chip areas and thereby preserving operational reliability in the 3D stacked structure
2Productivity
If test circuits are placed in the scribe lane area to improve integration, then the degree of integration is improved, but manufacturing precision deteriorates due to the complexity of placing functional circuits in non-traditional areas
Solution Approach 1:
Different functional areas are assigned to different regions of the scribe lane: cross areas contain test circuits for electrical testing, while line areas contain dummy structures for mechanical support and stress absorption. This local differentiation allows each region to be optimized for its specific function, maintaining manufacturing precision while achieving high integration
Solution Approach 2:
The scribe lane area serves as an intermediary zone between the chip areas. By placing test circuits in the cross areas of the scribe lane, the patent creates a buffer zone that facilitates testing without interfering with the chip fabrication process, thereby maintaining manufacturing precision while improving integration
3Reliability
If dummy structures are formed in the scribe lane area to protect chip areas during cutting, then reliability is improved, but device complexity increases due to additional structural elements
Solution Approach 1:
The protective function is extracted from the chip areas and relocated to the scribe lane area. Dummy structures are formed only in the line areas of the scribe lane, separating the stress absorption function from the chip areas. This extraction reduces the complexity within the chip areas while maintaining overall structural stability
Solution Approach 2:
The dummy structures in the scribe lane area serve as disposable protective elements that are sacrificed during the cutting process. These structures absorb stress and protect the chip areas, and are subsequently removed or discarded after serving their protective purpose, thereby maintaining reliability without permanently increasing device complexity
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a test circuit in a cross area of a scribe lane area disposed between chip areas of a substrate. The method also includes forming a first dummy structure on the test circuit, forming a test pad in a line area of the scribe lane area of the substrate, and cutting the substrate along the scribe lane area.