Scribe Lane Via Structure for Low-Impact Wafer Dicing

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

The dicing process for semiconductor wafers is hindered by structures such as test element groups (TEGs) on the scribe lane region, making it difficult to efficiently separate semiconductor chips while minimizing impact on their electrical characteristics.

Innovation Solution

A semiconductor device design that includes a substrate with a scribe lane region featuring alternating layers of low-k dielectric and higher dielectric constant insulating interlayers, conductive structures, and vias, which guide the dicing process and absorb the impact to prevent damage to the chips.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If TEG and other structures are formed on the scribe lane region, then electrical characteristics testing and chip alignment are enabled, but the dicing process becomes difficult and impact spreads to semiconductor chips

Engineering Contradiction:

Improveelectrical characteristics testingVSAvoiddicing process

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The scribe lane region is segmented into multiple layers with different dielectric constants (low-k dielectric interlayer structure and high-k dielectric interlayer), creating distinct zones that guide the dicing blade while protecting the chip regions. This segmentation allows the dicing process to follow a predetermined path through the scribe lane without deviating into chip areas.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Conductive structures are introduced as intermediary elements within the scribe lane region, extending through the insulating interlayer structures. These conductive structures serve as mediators that both enable electrical testing functions and provide physical guidance for the dicing process, absorbing impact and preventing it from reaching the semiconductor chips.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If dicing is performed through the scribe lane region, then semiconductor chips are separated, but impact from the dicing process spreads to the chips and damages their electrical characteristics

Engineering Contradiction:

Improvechip separationVSAvoidelectrical characteristics

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The low-k dielectric interlayer structure is positioned in the scribe lane region ahead of the chip areas, serving as a cushioning layer that absorbs the impact of the dicing blade before it can reach the semiconductor chips. This prior cushioning protects the electrical characteristics of the chips while still allowing effective separation.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The dicing impact, which would normally be harmful to the chips, is converted into a beneficial force by directing it through the scribe lane region containing the low-k dielectric and conductive structures. The impact is absorbed and dissipated in the scribe lane, transforming a potentially damaging effect into a protective mechanism.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

3Reliability

If low-k dielectric material is used in the scribe lane region, then impact is absorbed and chip protection is improved, but manufacturing complexity increases due to multiple insulating interlayer structures

Engineering Contradiction:

Improvechip protectionVSAvoidinsulating interlayer structures

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The multiple insulating interlayer structures (low-k dielectric and high-k dielectric layers) serve multiple functions simultaneously: they provide mechanical guidance for the dicing blade, absorb impact to protect chips, enable electrical testing through conductive structures, and maintain structural integrity. This multi-functionality justifies the increased structural complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent employs composite material structures combining low-k dielectric materials and high-k dielectric materials in alternating layers. This composite approach optimizes both the impact absorption properties (low-k) and the structural/stability properties (high-k), achieving superior chip protection while managing the complexity through material composition rather than sheer layer count.

Inventive Principle:

Principle #40Composite materials

Data Source

PatentUS11876043B2Semiconductor devices having vias on a scribe lane region

Publication Date: 2024.01.16 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor device includes a substrate having a chip region and a scribe lane region having first edges extending in a first direction and second edges extending in a second direction, a first insulating interlayer structure on the scribe lane region and including a low-k dielectric material, first conductive structures on a portion of the scribe lane region adjacent one of the first edges and each extending through the first insulating interlayer structure in a vertical direction and extending in the first direction, a second insulating interlayer on the first insulating interlayer structure and including a material having a dielectric constant greater than that of the first insulating interlayer structure, first vias each extending in the first direction through the second insulating interlayer to contact one of the first conductive structures, and a first wiring commonly contacting upper surfaces of the first vias.