Scribe Line Crack Guide Structures for Low-k Dicing Reliability
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Solution Overview
Problem
Low-k insulating materials in semiconductor devices, such as silicon oxycarbide and silicon carbonitride, exhibit weak thermo-mechanical characteristics, leading to adhesion issues and brittleness, which can result in cracks during the dicing process, reducing yield and increasing fabrication complexity and cost.
Innovation Solution
Incorporating a scribe center region with a crack guide structure and crack mitigation structures, including lines and vias with higher hardness than the insulating films, to guide excessive force away from semiconductor chips and prevent crack propagation, thereby reducing the risk of cracks reaching the element formation region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If low-k insulating materials are used to reduce parasitic capacitance, then high-speed operations are achieved, but thermo-mechanical characteristics deteriorate leading to adhesion issues and brittleness
Solution Approach 1:
The patent applies local quality by forming a reinforced insulating film structure specifically in the scribe region where cracks are most likely to occur during dicing, while using standard low-k materials in the chip body. This localized reinforcement approach maintains the high-speed performance benefits of low-k materials in the functional areas while providing enhanced mechanical strength where needed for crack resistance.
Solution Approach 2:
The patent implements preliminary action by pre-forming a reinforced insulating film structure in the scribe region before the dicing process. This preventive measure ensures that the structure is already strengthened against potential cracks before the mechanical stress of dicing occurs, thereby preventing adhesion issues and crack propagation without affecting the operational speed of the device.
2Loss of energy
If low-k insulating materials are used, then parasitic capacitance is reduced, but cracks propagate during dicing process, reducing yield
Solution Approach 1:
The patent applies local quality by forming a reinforced insulating film structure specifically in the scribe region where cracks are most likely to occur during dicing, while using standard low-k materials in the chip body. This localized reinforcement approach maintains the high-speed performance benefits of low-k materials in the functional areas while providing enhanced mechanical strength where needed for crack resistance.
Solution Approach 2:
The patent implements preliminary action by pre-forming a reinforced insulating film structure in the scribe region before the dicing process. This preventive measure ensures that the structure is already strengthened against potential cracks before the mechanical stress of dicing occurs, thereby preventing adhesion issues and crack propagation without affecting the operational speed of the device.
3Reliability
If grooves are formed in scribe region to reduce cracks, then crack propagation is mitigated, but fabrication complexity and cost increase
Solution Approach 1:
The patent applies parameter changes by modifying the physical and chemical properties of the insulating film in the scribe region through controlled carbon content adjustment and selective reinforcement. Instead of adding complex groove structures, the invention changes the material parameters (carbon concentration, film density) to achieve enhanced crack resistance, thereby maintaining fabrication simplicity while improving reliability.
Solution Approach 2:
The patent employs composite materials by creating a reinforced insulating film with specific carbon-containing compositions that combine the low dielectric constant properties of low-k materials with enhanced mechanical strength. This composite approach allows the film to simultaneously provide electrical performance and structural reinforcement without requiring additional groove formation processes.
Data Source
AI summary
Apparatuses including structures in scribe lines are described. An example apparatus includes: a first chip and a second chip; a scribe region between the first chip and the second chip; a crack guide region in the scribe region, the crack guide region including a dicing line along which the first chip and the second chip are to be divided; and a structure disposed in the crack guide region and extending along the dicing line.