Semiconductor Scribe Line Etching for Clean Stealth Dicing
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Solution Overview
Problem
The metal pads on the top of scribe line regions in semiconductor wafers cause unwanted crack propagation and chipping during chip separation.
Innovation Solution
A method involving a series of etching processes, including dry and wet etching, to remove the interconnect structure and expose the substrate, followed by a back side stealth dicing process to induce cracks for chip separation, minimizing damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal pads are present on the top of scribe line regions, then electrical connectivity is maintained, but crack propagation and chipping occur during chip separation
Solution Approach 1:
The patent removes the metal pad from the scribe line region by performing a first dry etching process to remove the top metalization layer and subsequent wet etching processes to remove the interconnect structure. This extraction eliminates the harmful effect of metal pads causing crack propagation during chip separation, while the electrical connectivity is maintained through the remaining interconnect structures within the device regions.
2Object-affected harmful factors
If the top metalization layer is removed to eliminate metal pads, then crack propagation is reduced, but the interconnect structure must be exposed requiring additional etching steps
Solution Approach 1:
The patent segments the removal process into distinct stages: first dry etching to remove the top metalization layer and expose the interconnect structure, followed by wet etching processes to remove the interconnect structure. This segmentation allows for selective removal of different layers with appropriate etching methods, achieving complete removal of metal pads while maintaining control over the process.
Solution Approach 2:
The first dry etching process is performed as a preliminary action to remove the top metalization layer and expose the interconnect structure before the wet etching process. This preliminary exposure enables the subsequent wet etchant to effectively access and remove the interconnect structure, ensuring complete elimination of metal pads that could cause crack propagation.
3Manufacturing precision
If multiple wet etching processes are performed to completely remove the interconnect structure, then clean separation is achieved, but processing time increases
Solution Approach 1:
The patent uses different etchants as intermediaries for different removal tasks: a first wet etchant specifically targets and removes the interconnect structure after exposure, and a second wet etchant completes the removal process. These intermediary chemical agents enable selective and complete removal of metal-containing structures, achieving clean separation that prevents crack propagation during chip separation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces chip separation issues such as chipping and crack propagation by thinning the scribe line layers and facilitating clean separation of semiconductor chips.
Implementation Method 1
performing a first dry etching process to remove a top metalization layer
Implementation Method 2
performing a first wet etching process using a first etchant to remove a filling layer of the interconnect structure
Implementation Method 3
performing a second wet etching process using a second etchant to remove a glue layer of the interconnect structure
Implementation Method 4
performing a back side stealth dicing process to induce cracks in a substrate from a back side to a front side so as to separate a semiconductor wafer into the semiconductor chips
Data Source
AI summary
The present disclosure provides a method of manufacturing semiconductor chips. The method includes performing a first dry etching process to remove a top metalization layer such that a portion of an interconnect structure is exposed by a scribe line opening after the top metalization layer is removed, wherein the interconnect structure is embedded in a dielectric layer. Next, a first wet etching process using a first etchant is performed to remove a filling layer of the interconnect structure. After performing the first wet etching process, a second wet etching process using a second etchant is performed to remove a glue layer of the interconnect structure. After performing a second wet etching process, a back side stealth dicing process is performed to induce cracks in a substrate from a back side to a front side so as to separate a semiconductor wafer into the semiconductor chips.